Power ISA™ Version 2.03 - Power.org

Version 2.03
3.3 Fixed-Point Processor Instructions
3.3.1 Fixed-Point Storage Access Instructions
The Storage Access instructions compute the effective
address (EA) of the storage to be accessed as
described in Section 1.10.3 on page 21.
Programming Note
The la extended mnemonic permits computing an
effective address as a Load or Store instruction
would, but loads the address itself into a GPR
rather than loading the value that is in storage at
that address.
Programming Note
The DS field in DS-form Storage Access instructions
is a word offset, not a byte offset like the D
field in D-form Storage Access instructions. However,
for programming convenience, Assemblers
should support the specification of byte offsets for
both forms of instruction.
3.3.1.1 Storage Access Exceptions
Storage accesses will cause the system data storage
error handler to be invoked if the program is not
allowed to modify the target storage (Store only), or if
the program attempts to access storage that is unavailable.
3.3.2 Fixed-Point Load Instructions
The byte, halfword, word, or doubleword in storage
addressed by EA is loaded into register RT.
Many of the Load instructions have an “update” form, in
which register RA is updated with the effective address.
For these forms, if RA≠0 and RA≠RT, the effective
address is placed into register RA and the storage element
(byte, halfword, word, or doubleword) addressed
by EA is loaded into RT.
Programming Note
In some implementations, the Load Algebraic and
Load with Update instructions may have greater
latency than other types of Load instructions.
Moreover, Load with Update instructions may take
longer to execute in some implementations than
the corresponding pair of a non-update Load
instruction and an Add instruction.
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Power ISA -- Book I