Power ISA™ Version 2.03 - Power.org

Version 2.03
Vector Unpack Low Pixel
VX-form
Vector Unpack Low Signed Byte VX-form
vupklpx
VRT,VRB
vupklsb
VRT,VRB
4 VRT /// VRB 974
0 6 11 16 21 31
do i=0 to 63 by 16
VRT i×2:i×2+7 EXTS((VRB) i+64 )
VRT i×2+8:i×2+15 EXTZ((VRB) i+65:i+69 )
VRT i×2+16:i×2+23 EXTZ((VRB) i+70:i+74 )
VRT i×2+24:i×2+31 EXTZ((VRB) i+75:i+79 )
For each vector element i from 0 to 3, do the following.
Halfword element i+4 in VRB is unpacked as follows.
- sign-extend bit 0 of the halfword to 8 bits
- zero-extend bits 1:5 of the halfword to 8 bits
- zero-extend bits 6:10 of the halfword to 8 bits
- zero-extend bits 11:15 of the halfword to 8 bits
The result is placed in word element i of VRT.
Special Registers Altered:
None
do i=0 to 63 by 8
VRT i×2:i×2+15 EXTS((VRB) i+64:i+71 )
For each vector element i from 0 to 7, do the following.
Signed-integer byte element i+8 in VRB is
sign-extended to produce a signed-integer halfword
and placed into halfword element i in VRT.
Special Registers Altered:
None
Vector Unpack Low Signed Halfword
VX-form
vupklsh
4 VRT /// VRB 654
0 6 11 16 21 31
VRT,VRB
4 VRT /// VRB 718
0 6 11 16 21 31
do i=0 to 63 by 16
VRT i×2:i×2+31 EXTS((VRB) i+64:i+79 )
For each vector element i from 0 to 3, do the following.
Signed-integer halfword element i+4 in VRB is
sign-extended to produce a signed-integer word
and placed into word element i in VRT.
Special Registers Altered:
None
148
Power ISA -- Book I