Power ISA™ Version 2.03 - Power.org

Version 2.03
Time-out. No exception recorded in TSR WIS .
Set TSR ENW so next time-out will cause exception.
TSR ENW,WIS =0b00
(2) SW Loop
TSR ENW,WIS =0b10
(1) Watchdog
Interrupt
Handler
(2) Watchdog
Interrupt
Handler
(3) SW Loop
Time-out. WDT exception recorded in TSR WIS
WDT interrupt will occur if enabled by
TCR WIE and MSR CE
TSR ENW,WIS =0b01
TSR ENW,WIS =0b11
Time-out
If TCR WRC ≠00 then RESET, including
TSR WRS ← TCR WRC
TCR WRC ← 0b00
Time-out. Set TSR ENW
so next time-out will
cause reset
Figure 23. Watchdog State Machine
Enable
Next WDT
(TSR ENW )
WDT Status
(TSR WIS )
Figure 24. Watchdog Timer Controls
Action when timer interval expires
0 0 Set Enable Next Watchdog Timer (TSR ENW =1).
0 1 Set Enable Next Watchdog Timer (TSR ENW =1).
1 0 Set Watchdog Timer interrupt status bit (TSR WIS =1).
If Watchdog Timer interrupt is enabled (TCR WIE =1 and
MSR CE =1), then interrupt.
1 1 Cause Watchdog Timer reset action specified by
TCR WRC . Reset will copy pre-reset TCR WRC into
TSR WRS , then clear TCR WRC .
The controls described in the above table imply three
different modes of operation that a programmer might
select for the Watchdog Timer. Each of these modes
assumes that TCR WRC has been set to allow processor
reset by the Watchdog facility:
1. Always take the Watchdog Timer interrupt when
pending, and never attempt to prevent its occurrence.
In this mode, the Watchdog Timer interrupt
caused by a first time-out is used to clear TSR WIS
so a second time-out never occurs. TSR ENW is not
cleared, thereby allowing the next time-out to
cause another interrupt.
2. Always take the Watchdog Timer interrupt when
pending, but avoid when possible. In this mode a
recurring code loop of reliable duration (or perhaps
a periodic interrupt handler such as the Fixed-
Interval Timer interrupt handler) is used to repeatedly
clear TSR ENW such that a first time-out
exception is avoided, and thus no Watchdog Timer
interrupt occurs. Once TSR ENW has been cleared,
software has between one and two full Watchdog
periods before a Watchdog exception will be
posted in TSR WIS . If this occurs before the software
is able to clear TSR ENW again, a Watchdog
Timer interrupt will occur. In this case, the Watchdog
Timer interrupt handler will then clear both
TSR ENW and TSR WIS , in order to (hopefully) avoid
the next Watchdog Timer interrupt.
Chapter 7. Timer Facilities
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