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Version 2.03
RN Rounding Mode
00 Round to Nearest
01 Round toward Zero
10 Round toward +Infinity
11 Round toward -Infinity
Let Z be the intermediate arithmetic result or the operand
of a convert operation. If Z can be represented
exactly in the target format, then the result in all rounding
modes is Z as represented in the target format. If Z
cannot be represented exactly in the target format, let
Z1 and Z2 bound Z as the next larger and next smaller
numbers representable in the target format. Then Z1 or
Z2 can be used to approximate the result in the target
format.
Figure 50 shows the relation of Z, Z1, and Z2 in this
case. The following rules specify the rounding in the
four modes. “LSB” means “least significant bit”.
Z2
Z
Z1
Negative values
By Incrementing LSB of Z
Infinitely Precise Value
By Truncating after LSB
0
Positive values
Z2
Z
Z1
Figure 50. Selection of Z1 and Z2
Round to Nearest
Choose the value that is closer to Z (Z1 or
Z2). In case of a tie, choose the one that is
even (least significant bit 0).
Round toward Zero
Choose the smaller in magnitude (Z1 or Z2).
Round toward +Infinity
Choose Z1.
Round toward -Infinity
Choose Z2.
See Section 4.5.1, “Execution Model for IEEE Operations”
on page 103 for a detailed explanation of rounding.
4.4 Floating-Point Exceptions
This architecture defines the following floating-point
exceptions:
Invalid Operation Exception
SNaN
Infinity-Infinity
Infinity÷Infinity
Zero÷Zero
Infinity×Zero
Invalid Compare
Software-Defined Condition
Invalid Square Root
Invalid Integer Convert
Zero Divide Exception
Overflow Exception
Underflow Exception
Inexact Exception
These exceptions, other than Invalid Operation Exception
due to Software-Defined Condition, may occur during
execution of computational instructions. An Invalid
Operation Exception due to Software-Defined Condition
occurs when a Move To FPSCR instruction sets
FPSCR VXSOFT to 1.
Each floating-point exception, and each category of
Invalid Operation Exception, has an exception bit in the
FPSCR. In addition, each floating-point exception has a
corresponding enable bit in the FPSCR. The exception
bit indicates occurrence of the corresponding exception.
If an exception occurs, the corresponding enable
bit governs the result produced by the instruction and,
in conjunction with the FE0 and FE1 bits (see page 99),
whether and how the system floating-point enabled
exception error handler is invoked. (In general, the
enabling specified by the enable bit is of invoking the
system error handler, not of permitting the exception to
occur. The occurrence of an exception depends only on
the instruction and its inputs, not on the setting of any
control bits. The only deviation from this general rule is
that the occurrence of an Underflow Exception may
depend on the setting of the enable bit.)
A single instruction, other than mtfsfi or mtfsf, may set
more than one exception bit only in the following cases:
Inexact Exception may be set with Overflow
Exception.
Inexact Exception may be set with Underflow
Exception.
Invalid Operation Exception (SNaN) is set with
Invalid Operation Exception (∞×0) for Multiply-Add
instructions for which the values being multiplied
are infinity and zero and the value being added is
an SNaN.
Invalid Operation Exception (SNaN) may be set
with Invalid Operation Exception (Invalid Compare)
for Compare Ordered instructions.
Invalid Operation Exception (SNaN) may be set
with Invalid Operation Exception (Invalid Integer
Convert) for Convert To Integer instructions.
98
Power ISA -- Book I