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interrupt
The act of changing the machine state in response
to an exception, as described in Chapter
5. “Interrupts and Exceptions” on page 541.
trap interrupt
An interrupt that results from execution of a Trap
instruction.
Additional exceptions to the rule that the processor
obeys the sequential execution model, beyond
those described in the section entitled “Instruction
Fetching” in Book I, are the following.
- A System Reset or Machine Check interrupt
may occur. The determination of whether an
instruction is required by the sequential execution
model is not affected by the potential
occurrence of a System Reset or Machine
Check interrupt. (The determination is
affected by the potential occurrence of any
other kind of interrupt.)
- A context-altering instruction is executed
(Chapter 10. “Synchronization Requirements
for Context Alterations” on page 603). The
context alteration need not take effect until the
required subsequent synchronizing operation
has occurred.
hardware
Any combination of hard-wired implementation,
emulation assist, or interrupt for software assistance.
In the last case, the interrupt may be to an
architected location or to an implementationdependent
location. Any use of emulation assists
or interrupts to implement the architecture is implementation-dependent.
/, //, ///, ... denotes a field that is reserved in an
instruction, in a register, or in an architected storage
table.
?, ??, ???, ... denotes a field that is implementation-dependent
in an instruction, in a register, or in
an architected storage table.
1.3.2 Reserved Fields
Some fields of certain architected registers may be written
to automatically by the processor, e.g., Reserved
bits in System Registers. When the processor writes to
such a register, the following rules are obeyed.
Unless otherwise stated, no defined field other
than the one(s) the processor is specifically updating
are modified.
Contents of reserved fields are either preserved by
the processor or written as zero.
The reader should be aware that reading and writing of
some of these registers (e.g., the MSR) can occur as a
side effect of processing an interrupt and of returning
from an interrupt, as well as when requested explicitly
by the appropriate instruction (e.g., mtmsr instruction).
1.4 General Systems Overview
The processor or processor unit contains the sequencing
and processing controls for instruction fetch,
instruction execution, and interrupt action. Most implementations
also contain data and instruction caches.
Instructions that the processing unit can execute fall
into the following classes:
instructions executed in the Branch Processor
instructions executed in the Fixed-Point Processor
instructions executed in the Floating-Point Processor
instructions executed in the Vector Processor
instructions executed in an Auxiliary Processor
other instructions executed by the processor
Almost all instructions executed in the Branch Processor,
Fixed-Point Processor, Floating-Point Processor,
and Vector Processor are nonprivileged and are
described in Book I. Book I may describe additional
nonprivileged instructions (e.g., Book II describes some
nonprivileged instructions for cache management).
Instructions executed in an Auxiliary Processor are
implementation-dependent. Instructions related to the
supervisor mode, control of processor resources, control
of the storage hierarchy, and all other privileged
instructions are described here or are implementationdependent.
1.5 Exceptions
The following augments the exceptions defined in Book
I that can be caused directly by the execution of an
instruction:
the execution of a floating-point instruction when
MSR FP =0 (Floating-Point Unavailable interrupt)
execution of an instruction that causes a debug
event (Debug interrupt).
the execution of an auxiliary processor instruction
when the auxiliary instruction is unavailable (Auxiliary
Processor Unavailable interrupt)
the execution of a Vector, SPE, or Embedded
Floating-Point instruction when MSR SPV =0 (SPE/
Embedded Floating-Point/Vector Unavailable interrupt)
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Power ISA -- Book III-E