Power ISA™ Version 2.03 - Power.org

Version 2.03
Notes:
1. The effect of changing the EE bit is immediate,
even if the mtmsr[d] instruction is not context synchronizing
(i.e., even if L=1).
If an mtmsr[d] instruction sets the EE bit to 0,
neither an External interrupt nor a Decrementer
interrupt occurs after the mtmsr[d] is
executed.
If an mtmsr[d] instruction changes the EE bit
from 0 to 1 when an External, Decrementer, or
higher priority exception exists, the corresponding
interrupt occurs immediately after
the mtmsr[d] is executed, and before the next
instruction is executed in the program that set
EE to 1.
If a hypervisor executes the mtmsr[d] instruction
that sets the EE bit to 0, a Hypervisor
Decrementer interrupt does not occur after
mtmsr[d] is executed as long as the processor
remains in hypervisor state.
If the hypervisor executes an mtmsr[d]
instruction that changes the EE bit from 0 to 1
when a Hypervisor Decrementer or higher priority
exception exists, the corresponding interrupt
occurs immediately after the mtmsr[d]
instruction is executed, and before the next
instruction is executed, provided HDICE is 1.
2. Synchronization requirements for this instruction
are implementation-dependent.
3. SDR1 must not be altered when MSR DR =1 or
MSR IR =1; if it is, the results are undefined.
4. A ptesync instruction is required before the mtspr
instruction because (a) SDR1 identifies the Page
Table and thereby the location of Reference and
Change bits, and (b) on some implementations,
use of SDR1 to update Reference and Change bits
may be independent of translating the virtual
address. (For example, an implementation might
identify the PTE in which to update the Reference
and Change bits in terms of its offset in the Page
Table, instead of its real address, and then add the
Page Table address from SDR1 to the offset to
determine the real address at which to update the
bits.) To ensure that Reference and Change bits
are updated in the correct Page Table, SDR1 must
not be altered until all Reference and Change bit
updates associated with address translations that
were performed, by the processor executing the
mtspr instruction, before the mtspr instruction is
executed have been performed with respect to that
processor. A ptesync instruction guarantees this
synchronization of Reference and Change bit
updates, while neither a context synchronizing
operation nor the instruction fetching mechanism
does so.
5. For data accesses, the context synchronizing
instruction before the tlbie, tlbiel, or tlbia instruction
ensures that all preceding instructions that
access data storage have completed to a point at
which they have reported all exceptions they will
cause.
The context synchronizing instruction after the
tlbie, tlbiel, or tlbia instruction ensures that storage
accesses associated with instructions following
the context synchronizing instruction will not
use the TLB entry(s) being invalidated.
(If it is necessary to order storage accesses associated
with preceding instructions, or Reference
and Change bit updates associated with preceding
address translations, with respect to subsequent
data accesses, a ptesync instruction must also be
used, either before or after the tlbie, tlbiel, or tlbia
instruction. These effects of the ptesync instruction
are described in the last paragraph of Note 8.)
6. The notation “{ptesync,CSI}” denotes an instruction
sequence. Other instructions may be interleaved
with this sequence, but these instructions
must appear in the order shown.
No software synchronization is required before the
Store instruction because (a) stores are not performed
out-of-order and (b) address translations
associated with instructions preceding the Store
instruction are not performed again after the store
has been performed (see Section 5.5). These
properties ensure that all address translations
associated with instructions preceding the Store
instruction will be performed using the old contents
of the PTE.
The ptesync instruction after the Store instruction
ensures that all searches of the Page Table that
are performed after the ptesync instruction completes
will use the value stored (or a value stored
subsequently). The context synchronizing instruction
after the ptesync instruction ensures that any
address translations associated with instructions
following the context synchronizing instruction that
were performed using the old contents of the PTE
will be discarded, with the result that these
address translations will be performed again and, if
there is no corresponding entry in any implementation-specific
address translation lookaside information,
will use the value stored (or a value stored
subsequently).
The ptesync instruction also ensures that all storage
accesses associated with instructions preceding
the ptesync instruction, and all Reference and
Change bit updates associated with additional
address translations that were performed, by the
processor executing the ptesync instruction,
before the ptesync instruction is executed, will be
performed with respect to any processor or mechanism,
to the extent required by the associated
Memory Coherence Required attributes, before
any data accesses caused by instructions follow-
Chapter 10. Synchronization Requirements for Context Alterations
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