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<strong>Version</strong> <strong>2.03</strong><br />

Chapter 10. Synchronization Requirements for Context<br />

Alterations<br />

Changing the contents of certain System Registers, the<br />

contents of SLB entries, or the contents of other system<br />

resources that control the context in which a program<br />

executes can have the side effect of altering the context<br />

in which data addresses and instruction addresses<br />

are interpreted, and in which instructions are executed<br />

and data accesses are performed. For example,<br />

changing MSR IR from 0 to 1 has the side effect of<br />

enabling translation of instruction addresses. These<br />

side effects need not occur in program order, and<br />

therefore may require explicit synchronization by software.<br />

(Program order is defined in Book II.)<br />

An instruction that alters the context in which data<br />

addresses or instruction addresses are interpreted, or<br />

in which instructions are executed or data accesses are<br />

performed, is called a context-altering instruction. This<br />

chapter covers all the context-altering instructions. The<br />

software synchronization required for them is shown in<br />

Table 1 (for data access) and Table 2 (for instruction<br />

fetch and execution).<br />

The notation “CSI” in the tables means any context<br />

synchronizing instruction (e.g., sc, isync, or rfid). A<br />

context synchronizing interrupt (i.e., any interrupt<br />

except non-recoverable System Reset or non-recoverable<br />

Machine Check) can be used instead of a context<br />

synchronizing instruction. If it is, phrases like “the synchronizing<br />

instruction”, below, should be interpreted as<br />

meaning the instruction at which the interrupt occurs. If<br />

no software synchronization is required before (after) a<br />

context-altering instruction, “the synchronizing instruction<br />

before (after) the context-altering instruction”<br />

should be interpreted as meaning the context-altering<br />

instruction itself.<br />

If a sequence of instructions contains context-altering<br />

instructions and contains no instructions that are<br />

affected by any of the context alterations, no software<br />

synchronization is required within the sequence.<br />

Programming Note<br />

Sometimes advantage can be taken of the fact that<br />

certain events, such as interrupts, and certain<br />

instructions that occur naturally in the program,<br />

such as the rfid that returns from an interrupt handler,<br />

provide the required synchronization.<br />

No software synchronization is required before or after<br />

a context-altering instruction that is also context synchronizing<br />

or when altering the MSR in most cases<br />

(see the tables). No software synchronization is<br />

required before most of the other alterations shown in<br />

Table 2, because all instructions preceding the contextaltering<br />

instruction are fetched and decoded before the<br />

context-altering instruction is executed (the processor<br />

must determine whether any of these preceding<br />

instructions are context synchronizing).<br />

Unless otherwise stated, the material in this chapter<br />

assumes a uniprocessor environment.<br />

The synchronizing instruction before the context-altering<br />

instruction ensures that all instructions up to and<br />

including that synchronizing instruction are fetched and<br />

executed in the context that existed before the alteration.<br />

The synchronizing instruction after the contextaltering<br />

instruction ensures that all instructions after<br />

that synchronizing instruction are fetched and executed<br />

in the context established by the alteration. Instructions<br />

after the first synchronizing instruction, up to and<br />

including the second synchronizing instruction, may be<br />

fetched or executed in either context.<br />

Chapter 10. Synchronization Requirements for Context Alterations<br />

467

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