Power ISA™ Version 2.03 - Power.org

Version 2.03
Data Cache Block Touch for Store by
External PID X-form
dcbtstep
TH,RA,RB
31 / TH RA RB 255 /
0 6 7 11 16 21 31
Let the effective address (EA) be the sum (RA|0)+(RB).
The dcbtstep instruction provides a hint that the program
will probably soon store to the block containing
the byte addressed by EA. If the Cache Specification
category is supported, the nature of the hint depends
on the value of the TH field, as specified in
Section 3.2.2 of Book II. If the Cache Specification category
is not supported, the TH field is treated as a
reserved field.
If the block is in a storage location that is Caching
Inhibited or Guarded, then the hint is ignored.
The only operation that is “caused” by the dcbtstep
instruction is the providing of the hint. The actions (if
any) taken by the processor in response to the hint are
not considered to be “caused by” or “associated with”
the dcbtstep instruction (e.g., dcbtstep is considered
not to cause any data accesses). No means are provided
by which software can synchronize these actions
with the execution of the instruction stream. For example,
these actions are not ordered by the memory barrier
created by a sync instruction.
The dcbtstep instruction may complete before the
operation it causes has been performed.
The instruction is treated as a Load, except that no
interrupt occurs if a protection violation occurs.
The instruction is privileged.
The normal address translation mechanism is not used.
The contents of the EPLC register are used to provide
the context in which translation occurs. The following
substitutions are made for just the translation and
access control process:
EPLC EPR is used in place of MSR PR
EPLC EAS is used in place of MSR DS
EPLC EPID is used in place of all Process ID registers.
Special Registers Altered:
None
Extended Mnemonics:
Extended mnemonics are provided for the Data Cache
Block Touch for Store by External PID instruction so
that it can be coded with the TH value as the last operand
for all categories. .
Extended:
Equivalent to:
dcbtstctep RA,RB,TH dcbtstep for TH values of
0b0000 - 0b0111;
other TH values are invalid.
Programming Note
This instruction behaves identically to a dcbtst
instruction except for using the EPLC register to
provide the translation context.
Chapter 3. Fixed-Point Processor
513