Power ISA™ Version 2.03 - Power.org

Version 2.03
tor unit, meaning that it will stall vector instruction execution
until all preceding vector instructions are
complete and have updated the architectural machine
state. This is permitted in order to simplify implementation
of the sticky status bit (SAT) which would otherwise
be difficult to implement in an out-of-order execution
machine. The implication of this is that reading the
VSCR can be much slower than typical Vector instructions,
and therefore care must be taken in reading it, as
advised in Section 5.5.1, to avoid performance problems.
The mtvscr is context synchronizing. This implies that
all Vector instructions logically preceding an mtvscr in
the program flow will execute in the architectural context
(NJ mode) that existed prior to completion of the
mtvscr, and that all instructions logically following the
mtvscr will execute in the new context (NJ mode)
established by the mtvscr.
5.3.3 VR Save Register
The VR Save Register (VRSAVE) is a 32-bit register
provided for application and operating system use.
VRSAVE
32 63
Figure 59. VR Save Register
Programming Note
The VRSAVE register can be used to indicate
which VRs are currently being used by a program.
If this is done, the operating system could save
only those VRs when an “interrupt” occurs (see
Book III), and could restore only those VRs when
resuming the interrupted program.
If this approach is taken it must be applied rigorously;
if a program fails to indicate that a given VR
is in use, software errors may occur that will be difficult
to detect and correct because they are timing-dependent.
Some operating systems save and restore
VRSAVE only for programs that also use other vector
registers.
5.4 Vector Storage Access Operations
The Vector Storage Access instructions provide the
means by which data can be copied from storage to a
Vector Register or from a Vector Register to storage.
Instructions are provided that access byte, halfword,
word, and quadword storage operands. These instructions
differ from the fixed-point and floating-point Storage
Access instructions in that vector storage operands
are assumed to be aligned, and vector storage
accesses are performed as if the appropriate number
of low-order bits of the specified effective address (EA)
were zero. For example, the low-order bit of EA is
ignored for halfword Vector Storage Access instructions,
and the low-order four bits of EA are ignored for
quadword Vector Storage Access instructions. The
effect is to load or store the storage operand of the
specified length that contains the byte addressed by
EA.
If a storage operand is unaligned, additional instructions
must be used to ensure that the operand is correctly
placed in a Vector Register or in storage.
Instructions are provided that shift and merge the contents
of two Vector Registers, such that an unaligned
quadword storage operand can be copied between
storage and the Vector Registers in a relatively efficient
manner.
As shown in Figure 56, the elements in Vector Registers
are numbered; the high-order (or most significant)
byte element is numbered 0 and the low-order (or least
significant) byte element is numbered 15. The numbering
affects the values that must be placed into the permute
control vector for the Vector Permute instruction
in order for that instruction to achieve the desired
effects, as illustrated by the examples in the following
subsections.
A vector quadword Load instruction for which the effective
address (EA) is quadword-aligned places the byte
in storage addressed by EA into byte element 0 of the
target Vector Register, the byte in storage addressed
by EA+1 into byte element 1 of the target Vector Register,
etc. Similarly, a vector quadword Store instruction
for which the EA is quadword-aligned places the contents
of byte element 0 of the source Vector Register
into the byte in storage addressed by EA, the contents
of byte element 1 of the source Vector Register into the
byte in storage addressed by EA+1, etc.
Figure 60 shows an aligned quadword in storage.
Figure 61 shows the result of loading that quadword
into a Vector Register or, equivalently, shows the contents
that must be in a Vector Register if storing that
Vector Register is to produce the storage contents
shown in Figure 60.
When an aligned byte, halfword, or word storage operand
is loaded into a Vector Register, the element (byte,
132
Power ISA -- Book I