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Version 2.03
Divide Doubleword
XO-form
Divide Doubleword Unsigned XO-form
divd RT,RA,RB (OE=0 Rc=0)
divd. RT,RA,RB (OE=0 Rc=1)
divdo RT,RA,RB (OE=1 Rc=0)
divdo. RT,RA,RB (OE=1 Rc=1)
31 RT RA RB OE 489 Rc
0 6 11 16 21 22 31
dividend 0:63 (RA)
divisor 0:63 (RB)
RT dividend × divisor
The 64-bit dividend is (RA). The 64-bit divisor is (RB).
The 64-bit quotient of the dividend and divisor is placed
into register RT. The remainder is not supplied as a
result.
Both operands and the quotient are interpreted as
signed integers. The quotient is the unique signed integer
that satisfies
dividend = (quotient × divisor) + r
where 0 ≤ r < |divisor| if the dividend is nonnegative,
and -|divisor| < r ≤ 0 if the dividend is negative.
If an attempt is made to perform any of the divisions
0x8000_0000_0000_0000 ÷ -1
÷ 0
then the contents of register RT are undefined as are (if
Rc=1) the contents of the LT, GT, and EQ bits of CR
Field 0. In these cases, if OE=1 then OV is set to 1.
Special Registers Altered:
CR0
(if Rc=1)
SO OV
(if OE=1)
Programming Note
The 64-bit signed remainder of dividing (RA) by
(RB) can be computed as follows, except in the
case that (RA) = -2 63 and (RB) = -1.
divd RT,RA,RB # RT = quotient
mulld RT,RT,RB # RT = quotient×divisor
subf RT,RT,RA # RT = remainder
divdu RT,RA,RB (OE=0 Rc=0)
divdu. RT,RA,RB (OE=0 Rc=1)
divduo RT,RA,RB (OE=1 Rc=0)
divduo. RT,RA,RB (OE=1 Rc=1)
31 RT RA RB OE 457 Rc
0 6 11 16 21 22 31
dividend 0:63 (RA)
divisor 0:63 (RB)
RT dividend ÷ divisor
The 64-bit dividend is (RA). The 64-bit divisor is (RB).
The 64-bit quotient of the dividend and divisor is placed
into register RT. The remainder is not supplied as a
result.
Both operands and the quotient are interpreted as
unsigned integers, except that if Rc=1 the first three
bits of CR Field 0 are set by signed comparison of the
result to zero. The quotient is the unique unsigned
integer that satisfies
dividend = (quotient × divisor) + r
where 0 ≤ r < divisor.
If an attempt is made to perform the division
÷ 0
then the contents of register RT are undefined as are (if
Rc=1) the contents of the LT, GT, and EQ bits of CR
Field 0. In this case, if OE=1 then OV is set to 1.
Special Registers Altered:
CR0
(if Rc=1)
SO OV
(if OE=1)
Programming Note
The 64-bit unsigned remainder of dividing (RA) by
(RB) can be computed as follows.
divdu RT,RA,RB # RT = quotient
mulld RT,RT,RB # RT = quotient×divisor
subf RT,RT,RA # RT = remainder
Chapter 3. Fixed-Point Processor
63