Power ISA™ Version 2.03 - Power.org

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Version 2.03 E.3 Floating-Point Selection [Category: Floating-Point] This section gives examples of how the Floating Select instruction can be used to implement floating-point minimum and maximum functions, and certain simple forms of if-then-else constructions, without branching. The examples show program fragments in an imaginary, C-like, high-level programming language, and the corresponding program fragment using fsel and other Power ISA instructions. In the examples, a, b, x, y, and z are floating-point variables, which are assumed to be in FPRs fa, fb, fx, fy, and fz. FPR fs is assumed to be available for scratch space. Additional examples can be found in Section E.2, “Floating-Point Conversions [Category: Floating-Point]” on page 328. Warning: Care must be taken in using fsel if IEEE compatibility is required, or if the values being tested can be NaNs or infinities; see Section E.3.4. E.3.1 E.3.2 Comparison to Zero High-level language: Power ISA: Notes if a ≥ 0.0 then x y else x z if a > 0.0 then x y else x z if a = 0.0 then x y else x z fsel fx,fa,fy,fz (1) fneg fs,fa fsel fx,fs,fz,fy fsel fx,fa,fy,fz fneg fs,fa fsel fx,fs,fx,fz Minimum and Maximum E.3.3 Simple if-then-else Constructions (1,2) (1) High-level language: Power ISA: Notes x min(a,b) x max(a,b) fsub fs,fa,fb fsel fx,fs,fb,fa fsub fs,fa,fb fsel fx,fs,fa,fb (3,4,5) (3,4,5) High-level language: Power ISA: Notes if a ≥ b then x y else x z if a > b then x y else x z if a = b then x y else x z fsub fs,fa,fb fsel fx,fs,fy,fz fsub fs,fb,fa fsel fx,fs,fz,fy fsub fs,fa,fb fsel fx,fs,fy,fz fneg fs,fs fsel fx,fs,fx,fz (4,5) (3,4,5) (4,5) E.3.4 Notes The following Notes apply to the preceding examples and to the corresponding cases using the other three arithmetic relations (
Version 2.03 E.4 Vector Unaligned Storage Operations [Category: Vector] E.4.1 Loading a Unaligned Quadword Using Permute from Big-Endian Storage The following sequence of instructions copies the unaligned quadword storage operand into VRT. # Assumptions: # Rb != 0 and contents of Rb = 0xB lvx Vhi,0,Rb # load MSQ lvsl Vp,0,Rb # set permute control vector addi Rb,Rb,16 # address of LSQ lvx Vlo,0,Rb # load LSQ perm Vt,Vhi,Vlo,Vp # align the data Appendix E. Programming Examples 331
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® Power ISA Version 2.03 September
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Version 2.03 Preface The roots of t
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Version 2.03 Table of Contents Pref
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Version 2.03 Chapter 5. Vector Proc
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Version 2.03 D.8 Move To/From Speci
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Version 2.03 5.7.1 32-Bit Mode . .
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Version 2.03 4.6 Invalid Real Addre
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Version 2.03 8.6 Debugger Notify Ha
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Version 2.03 5.8 Fixed-Point Select
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Version 2.03 Figures Preface ......
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Version 2.03 40. MMU Control and St
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Version 2.03 Book I: Power ISA User
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Version 2.03 Chapter 1. Introductio
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Version 2.03 GPR, FPR, or VR (e.g.
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Version 2.03 SPR(x) Special Purpose
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Version 2.03 An instruction in a ca
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Version 2.03 CR 32 63 “Condition
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Version 2.03 1.6.3 SC-FORM 0 6 11 1
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Version 2.03 1.6.19 EVX-FORM 0 6 11
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Version 2.03 SPR (11:20) Field used
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Version 2.03 for each virtual page,
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Version 2.03 beq done loop: cmplwi
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Version 2.03 Chapter 2. Branch Proc
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Version 2.03 or (RB) (unsigned comp
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Version 2.03 Programming Note Many
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Version 2.03 Branch I-form Branch C
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Version 2.03 2.5 Condition Register
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Version 2.03 2.6 System Call Instru
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Version 2.03 Chapter 3. Fixed-Point
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Version 2.03 3.2.3 Program Priority
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Version 2.03 Load Byte and Zero D-f
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Version 2.03 Load Halfword Algebrai
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Version 2.03 3.3.2.1 64-bit Fixed-P
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Version 2.03 3.3.3 Fixed-Point Stor
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Version 2.03 Store Word D-form Stor
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Version 2.03 3.3.4 Fixed-Point Load
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Version 2.03 3.3.6 Fixed-Point Move
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Version 2.03 Store String Word Imme
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Version 2.03 3.3.8 Fixed-Point Arit
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Version 2.03 Subtract From Immediat
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Version 2.03 Add to Zero Extended X
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Version 2.03 Divide Word XO-form di
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Version 2.03 Divide Doubleword XO-f
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Version 2.03 Compare Logical Immedi
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Version 2.03 3.3.10.1 64-bit Fixed-
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Version 2.03 OR Immediate Shifted D
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Version 2.03 NOR X-form Equivalent
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Version 2.03 3.3.12.1 64-bit Fixed-
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Version 2.03 Rotate Left Word Immed
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Version 2.03 3.3.13.1.1 64-bit Fixe
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Version 2.03 Rotate Left Doubleword
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Version 2.03 Shift Right Algebraic
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Version 2.03 3.3.14 Move To/From Sy
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Version 2.03 Move To Condition Regi
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Version 2.03 3.3.14.1 Move To/From
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Version 2.03 Chapter 4. Floating-Po
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Version 2.03 the FPRs with no conve
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Version 2.03 59 Floating-Point Zero
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Version 2.03 due to the invalid ope
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Version 2.03 Programming Note The F
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Version 2.03 When an exception occu
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Version 2.03 When Invalid Operation
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Version 2.03 4.4.5 Inexact Exceptio
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Version 2.03 4.5.2 Execution Model
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Version 2.03 Load Floating-Point Si
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Version 2.03 4.6.3 Floating-Point S
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Version 2.03 Store Floating-Point D
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Version 2.03 4.6.4 Floating-Point M
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Version 2.03 Floating Multiply [Sin
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Version 2.03 Floating Reciprocal Sq
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Version 2.03 Floating Negative Mult
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Version 2.03 Floating Convert To In
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Version 2.03 Floating Round to Inte
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Version 2.03 4.6.8 Floating-Point S
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Version 2.03 Move To FPSCR Bit 0 X-
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Version 2.03 Chapter 5. Vector Proc
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Version 2.03 Quadword Word 0 Word 1
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Version 2.03 halfword, or word resp
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Version 2.03 5.5 Vector Integer Ope
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Version 2.03 If an exception occurs
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Version 2.03 5.7.2 Vector Load Inst
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Version 2.03 5.7.3 Vector Store Ins
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Version 2.03 5.7.4 Vector Alignment
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Version 2.03 Vector Pack Signed Hal
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Version 2.03 Vector Unpack High Pix
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Version 2.03 5.8.2 Vector Merge Ins
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Version 2.03 5.8.3 Vector Splat Ins
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Version 2.03 5.8.6 Vector Shift Ins
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Version 2.03 5.9 Vector Integer Ins
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Version 2.03 Vector Add Unsigned By
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Version 2.03 Vector Subtract Unsign
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Version 2.03 5.9.1.3 Vector Integer
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Version 2.03 Vector Multiply-Sum Si
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Version 2.03 Vector Minimum Signed
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Version 2.03 5.9.2 Vector Integer C
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Version 2.03 Vector Compare Greater
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Version 2.03 5.9.4 Vector Integer R
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Version 2.03 Vector Shift Right Alg
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Version 2.03 5.10 Vector Floating-P
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Version 2.03 5.10.2 Vector Floating
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Version 2.03 Vector Convert from Si
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Version 2.03 5.11 Vector Status and
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Version 2.03 Chapter 6. Signal Proc
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Version 2.03 has occurred in the up
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Version 2.03 If the exception is en
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Version 2.03 6.3.7 SPE Instructions
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Version 2.03 Vector Add Signed, Sat
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Version 2.03 Vector Compare Greater
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Version 2.03 Vector Divide Word Uns
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Version 2.03 Vector Load Double int
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Version 2.03 Vector Load Word into
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Version 2.03 Vector Load Word into
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Version 2.03 Initialize Accumulator
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Version 2.03 Vector Multiply Word L
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Version 2.03 Vector Multiply Word L
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Version 2.03 Vector Multiply Word S
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Version 2.03 Vector Multiply Word U
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Version 2.03 Vector Rotate Left Wor
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Version 2.03 Vector Shift Right Wor
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Version 2.03 Vector Store Word of T
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Version 2.03 Vector Subtract Unsign
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Version 2.03 Chapter 7. Embedded Fl
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Version 2.03 Denormalized numbers o
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Version 2.03 7.3 Embedded Floating-
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Version 2.03 Vector Floating-Point
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Version 2.03 Vector Floating-Point
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Version 2.03 Vector Convert Floatin
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Version 2.03 7.3.3 SPE.Embedded Flo
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Version 2.03 Floating-Point Single-
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Version 2.03 Floating-Point Single-
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Version 2.03 Convert Floating-Point
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Version 2.03 Floating-Point Double-
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Version 2.03 Floating-Point Double-
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Version 2.03 7.4 Embedded Floating-
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Version 2.03 B.3 List Insertion Thi
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Version 2.03 Book III-S: Power ISA
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Version 2.03 the execution of a Ve
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Version 2.03 Chapter 2. Logical Par
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Version 2.03 2.5 Logical Partition
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Version 2.03 3.3 Branch Processor I
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Version 2.03 4.3.5 Software-use SPR
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Version 2.03 4.4.2 OR Instruction o
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Version 2.03 Move To Special Purpos
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Version 2.03 Move To Machine State
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Version 2.03 Chapter 5. Storage Con
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Version 2.03 stream being executed)
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Version 2.03 5.7.2.3 Storage Contro
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Version 2.03 5.7.5 Virtual Address
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Version 2.03 5.7.6 Virtual to Real
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Version 2.03 A virtual page is mapp
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Version 2.03 The 62-bit real addres
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Version 2.03 not necessarily perfor
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Version 2.03 5.8 Storage Control At
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Version 2.03 5.9 Storage Control In
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Version 2.03 information used in ad
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Version 2.03 SLB Move From Entry VS
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Version 2.03 Move To Segment Regist
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Version 2.03 5.9.3.3 TLB Management
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Version 2.03 TLB Invalidate All tlb
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Version 2.03 Programming Note The e
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Version 2.03 Chapter 6. Interrupts
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Version 2.03 6.3 Interrupt Synchron
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Version 2.03 Programming Note For i
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Version 2.03 6.5 Interrupt Definiti
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Version 2.03 If the contents of the
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Version 2.03 to fetch a branch targ
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Version 2.03 Programming Note These
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Version 2.03 Execution resumes at e
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Version 2.03 6.8 Interrupt Prioriti
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Version 2.03 Chapter 7. Timer Facil
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Version 2.03 “Assembler Extended
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Version 2.03 Chapter 8. Debug Facil
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Version 2.03 Programming Note Proce
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Version 2.03 Chapter 9. External Co
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Version 2.03 Chapter 10. Synchroniz
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Version 2.03 Notes: 1. The effect o
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Version 2.03 Appendix A. Assembler
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Version 2.03 Appendix B. Example Pe
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Version 2.03 reflected in Performan
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Version 2.03 Programming Note Time
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Version 2.03 32 Contents of SIAR an
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Version 2.03 Appendix C. Example Tr
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Version 2.03 Appendix D. Interpreta
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Version 2.03 Book III-E: Power ISA
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Version 2.03 1.6 Synchronization Th
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Version 2.03 2.3 Branch Processor I
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Version 2.03 Return From Machine-Ch
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Version 2.03 3.3.4 External Process
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Version 2.03 3.4 Fixed-Point Proces
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Version 2.03 Move To Special Purpos
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Version 2.03 Move From Device Contr
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Version 2.03 3.4.2 External Process
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Version 2.03 Store Byte by External
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Version 2.03 Data Cache Block Store
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Version 2.03 Data Cache Block Touch
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Version 2.03 Load Floating-Point Do
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Version 2.03 Load Vector by Externa
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Version 2.03 4.6 Invalid Real Addre
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Version 2.03 SX Supervisor State Ex
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Version 2.03 MSR DS for data storag
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Version 2.03 4.7.4 Storage Access C
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Version 2.03 Programming Note This
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Version 2.03 Accesses to the same s
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Version 2.03 4.9.2 Cache Locking [C
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Version 2.03 4.9.2.3 Cache Locking
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Version 2.03 4.9.3 Synchronize Inst
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Version 2.03 TLB Search Indexed X-f
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Version 2.03 Chapter 5. Interrupts
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Version 2.03 5.2.3 Critical Save/Re
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Version 2.03 5.2.9 Exception Syndro
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Version 2.03 5.2.11.1 Machine Check
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Version 2.03 exception that generat
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Version 2.03 Programming Note For i
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Version 2.03 IVOR Interrupt Excepti
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Version 2.03 5.6.3 Data Storage Int
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Version 2.03 cessing system. Also,
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Version 2.03 MSR CM MSR CM is set t
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Version 2.03 CSRR0, CSRR1, MSR, and
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Version 2.03 5.6.17 SPE/Embedded Fl
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Version 2.03 5.6.21 Processor Doorb
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Version 2.03 5.8 Interrupt Ordering
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Version 2.03 5.8.2 Interrupt Order
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Version 2.03 5.9.1.5 Exception Prio
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Version 2.03 Chapter 6. Reset and I
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Version 2.03 Chapter 7. Timer Facil
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Version 2.03 7.3 Decrementer The De
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Version 2.03 Bit(s) Description 32:
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Version 2.03 Time-out. No exception
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Version 2.03 Chapter 8. Debug Facil
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Version 2.03 Programming Note There
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Version 2.03 Later, if the debug ex
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Version 2.03 whose direction will b
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Version 2.03 8.4.10 Critical Interr
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Version 2.03 34:35 Instruction Addr
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Version 2.03 40:41 Data Address Com
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Version 2.03 8.5.3 Instruction Addr
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Version 2.03 Chapter 9. Processor C
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Version 2.03 9.3 Processor Control
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Version 2.03 Chapter 10. Synchroniz
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Version 2.03 If an mtmsr, wrtee, or
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Version 2.03 Appendix A. Implementa
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Version 2.03 A.2.1.3 Instruction Ca
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Version 2.03 Instruction Cache Read
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Version 2.03 Appendix B. Assembler
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Version 2.03 Appendix C. Guidelines
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Version 2.03 Appendix D. Type FSL S
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Version 2.03 52:63 Next Victim (NV)
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Version 2.03 58 Default VLE Value (
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Version 2.03 D.2.5 MMU Configuratio
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Version 2.03 D.4.3 Invalidating TLB
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Version 2.03 D.6 Type FSL MMU Instr
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Version 2.03 TLB Synchronize XL-for
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Version 2.03 Appendix E. Example Pe
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Version 2.03 counter with an event
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Version 2.03 111 Threshold field is
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Version 2.03 E.5 Performance Monito
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Version 2.03 Book VLE: Power ISA Op
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Version 2.03 Chapter 1. Variable Le
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Version 2.03 1.4.6 R-form (16-bit M
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Version 2.03 UI (6:10 || 21:31, 11:
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Version 2.03 Chapter 2. VLE Storage
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Version 2.03 ESR MIF is set when an
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Version 2.03 Chapter 3. VLE Compati
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Version 2.03 Chapter 4. Branch Oper
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Version 2.03 4.2 Branch Instruction
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Version 2.03 Branch to Count Regist
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Version 2.03 Return From Machine Ch
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Version 2.03 4.4 Condition Register
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Version 2.03 Load Halfword Algebrai
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Version 2.03 5.2 Fixed-Point Store
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Version 2.03 Store Word D-form Stor
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Version 2.03 5.5 Fixed-Point Arithm
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Version 2.03 Add Scaled Immediate C
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Version 2.03 5.6 Fixed-Point Compar
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Version 2.03 Compare Logical Scaled
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Version 2.03 Compare Halfword Logic
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Version 2.03 OR (two operand) Immed
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Version 2.03 Extend Sign Byte Short
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Version 2.03 5.10 Fixed-Point Rotat
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Version 2.03 Shift Right Algebraic
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Version 2.03 Chapter 7. Additional
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Version 2.03 Appendix A. VLE Instru
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Version 2.03 Form Mode Dep. 1 Priv
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Version 2.03 Appendix B. VLE Instru
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Version 2.03 Appendices: Power ISA
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Version 2.03 Appendix A. Incompatib
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Version 2.03 In POWER bits 20:26
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Version 2.03 privilege: mfsr and mf
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Version 2.03 A.32 POWER2 Compatibil
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Version 2.03 Appendix B. Platform S
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Version 2.03 Appendix C. Complete S
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Version 2.03 decimal SPR 1 Register
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Version 2.03 Appendix D. Illegal In
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Version 2.03 Appendix E. Reserved I
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Version 2.03 Appendix F. Opcode Map
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Version 2.03 Table 2: Extended opco
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Version 2.03 Table 5 (Left-Center)
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Version 2.03 Table 5 (Right) Extend
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Version 2.03 Table 6 (Left-Center)
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Version 2.03 Table 6 (Right) Extend
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Version 2.03 Table 7. (Right) Exten
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Version 2.03 Table 8. (Right) Exten
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Version 2.03 761
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Version 2.03 763 Table 13. (Right)
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Version 2.03 765 Table 14. (Right)
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Version 2.03 Appendix G. Power ISA
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Version 2.03 Form Opcode Pri Ext Mo
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Version 2.03 Appendix H. Power ISA
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Version 2.03 Appendix I. Power ISA
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Version 2.03 Mode Dependency and Pr
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Version 2.03 Index A a bit 26 A-for
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Version 2.03 F FE 25, 92 FEX 91 FE0
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Version 2.03 instructions classes 1
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Version 2.03 Machine Status Save Re
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Version 2.03 See Logical Partitioni
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Version 2.03 Last Page - End of Doc
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Power ISA™ Version 2.03 - Power.org

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