Power ISA™ Version 2.03 - Power.org

Version 2.03
B.2.2 Lock Release and Export
Barriers
An “export barrier” is an instruction or sequence of
instructions that prevents the store that releases a lock
from being performed before stores caused by instructions
preceding the barrier have been performed. An
export barrier can be used to ensure that all stores to a
shared data structure protected by a lock will be performed
with respect to any other processor before the
store that releases the lock is performed with respect to
that processor.
B.2.2.1 Export Shared Storage and
Release Lock
A sync instruction can be used as an export barrier
independent of the storage control attributes (e.g.,
presence or absence of the Caching Inhibited attribute)
of the storage containing the shared data structure.
Because the lock must be in storage that is neither
Write Through Required nor Caching Inhibited, if the
shared data structure is in storage that is Write
Through Required or Caching Inhibited a sync instruction
must be used as the export barrier.
In this example it is assumed that the shared data
structure is in storage that is Caching Inhibited, the
address of the lock is in GPR 3, the value indicating
that the lock is free is in GPR 4, and the address of the
shared data structure is in GPR 9.
stw
sync
stw
r7,data1(r9)#store shared data (last)
#export barrier
r4,lock(r3)#release lock
The sync ensures that the store that releases the lock
will not be performed with respect to any other processor
until all stores caused by instructions preceding the
sync have been performed with respect to that processor.
The lwsync ensures that the store that releases the
lock will not be performed with respect to any other processor
until all stores caused by instructions preceding
the lwsync have been performed with respect to that
processor.
B.2.3
Safe Fetch
If a load must be performed before a subsequent store
(e.g., the store that releases a lock protecting a shared
data structure), a technique similar to the following can
be used.
In this example it is assumed that the address of the
storage operand to be loaded is in GPR 3, the contents
of the storage operand are returned in GPR 4, and the
address of the storage operand to be stored is in GPR
5.
lwz r4,0(r3)#load shared data
cmpw r4,r4 #set CR0 to “equal”
bne- $-8 #branch never taken
stw r7,0(r5)#store other shared data
An alternative is to use a technique similar to that
described in Section B.2.1.2, by causing the stw to
depend on the value returned by the lwz and omitting
the cmpw and bne-. The dependency could be created
by ANDing the value returned by the lwz with zero and
then adding the result to the value to be stored by the
stw. If both storage operands are in storage that is neither
Write Through Required nor Caching Inhibited,
another alternative is to replace the cmpw and bnewith
an lwsync instruction.
B.2.2.2 Export Shared Storage and
Release Lock using lwsync
If the shared data structure is in storage that is neither
Write Through Required nor Caching Inhibited, an
lwsync instruction can be used as the export barrier.
Using lwsync rather than sync will yield better performance
in most systems.
In this example it is assumed that the shared data
structure is in storage that is neither Write Through
Required nor Caching Inhibited, the address of the lock
is in GPR 3, the value indicating that the lock is free is
in GPR 4, and the address of the shared data structure
is in GPR 9.
stw
lwsync
stw
r7,data1(r9)#store shared data (last)
#export barrier
r4,lock(r3)#release lock
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Power ISA -- Book II