Power ISA™ Version 2.03 - Power.org

Version 2.03
Instruction Cache Block Touch and Lock
Set
X-form
Instruction Cache Block Lock Clear
X-form
icbtls
CT,RA,RB
icblc
CT,RA,RB
31 / CT RA RB 486 /
0 6 7 11 16 21 31
31 / CT RA RB 230 /
0 6 7 11 16 21 31
Let the effective address (EA) be the sum (RA|0)+(RB).
The icbtls instruction causes the block containing the
byte addressed by EA to be loaded and locked into the
instruction cache specified by CT, and provides a hint
that the program will probably soon execute code from
the block. See Section 3.2 of Book II for a definition of
the CT field.
If the block already exists in the cache, the block is
locked without refetching from memory. If the block is in
storage that is Caching Inhibited, no cache operation is
performed.
This instruction treated as a Load (see Section 3.2),
except that the system instruction storage error handler
is not invoked.
An unable-to-lock condition may occur (see Section
4.9.2.2.2), or an overlocking condition may occur (see
Section 4.9.2.2.1).
This instruction is privileged unless the Embedded
Cache Locking.User Mode category is supported. If the
Embedded Cache Locking.User Mode category is supported,
this instruction is privileged only if MSR UCLE =0.
Special registers altered:
None
Let the effective address (EA) be the sum (RA|0)+(RB).
The block containing the byte addressed by EA in the
instruction cache specified by the CT field is unlocked.
The instruction is treated as a Load.
An unable-to-unlock condition may occur (see Section
4.9.2.2.2). If the block containing the byte addressed by
EA is not locked in the specified cache, no cache operation
is performed.
This instruction is privileged unless the Embedded
Cache Locking.User Mode category is supported. If the
Embedded Cache Locking.User Mode category is supported,
this instruction is privileged only if MSR UCLE =0.
Special registers altered:
None
Data Cache Block Lock Clear
dcblc
CT,RA,RB
X-form
31 / CT RA RB 390 /
0 6 7 11 16 21 31
Let the effective address (EA) be the sum (RA|0)+(RB).
The block containing the byte addressed by EA in the
data cache specified by the CT field is unlocked.
The instruction is treated as a Load.
An unable-to-unlock condition may occur (see Section
4.9.2.2.2). If the block containing the byte addressed by
EA is not locked in the specified cache, no cache operation
is performed.
This instruction is privileged unless the Embedded
Cache Locking.User Mode category is supported. If the
Embedded Cache Locking.User Mode category is supported,
this instruction is privileged only if MSR UCLE =0.
Special registers altered:
None
Programming Note
The dcblc and icblc instructions are used to
remove locks previously set by the corresponding
lock set instructions.
536
Power ISA -- Book III-E