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Power ISA™ Version 2.03 - Power.org

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<strong>Version</strong> <strong>2.03</strong><br />

Vector Multiply Word Low Unsigned,<br />

Saturate, Integer and Accumulate into<br />

Words<br />

EVX-form<br />

evmwlusiaaw RT,RA,RB<br />

4 RT RA RB 1344<br />

0 6 11 16 21 31<br />

Vector Multiply Word Low Unsigned,<br />

Saturate, Integer and Accumulate<br />

Negative in Words<br />

EVX-form<br />

evmwlusianw RT,RA,RB<br />

4 RT RA RB 1472<br />

0 6 11 16 21 31<br />

temp 0:63 (RA) 0:31 × ui (RB) 0:31<br />

temp 0:63 EXTZ((ACC) 0:31 ) + EXTZ(temp 32:63 )<br />

ovh temp 31<br />

RT 0:31 SATURATE(ovh, 0, 0xFFFF_FFFF, 0xFFFF_FFFF,<br />

temp 32:63 )<br />

temp 0:63 (RA) 32:63 × ui (RB) 32:63<br />

temp 0:63 EXTZ((ACC) 32:63 ) + EXTZ(temp 32:63 )<br />

ovl temp 31<br />

RT 32:63 SATURATE(ovl, 0, 0xFFFF_FFFF,<br />

0xFFFF_FFFF, temp 32:63 )<br />

ACC 0:63 (RT) 0:63<br />

SPEFSCR OVH ovh<br />

SPEFSCR OV ovl<br />

SPEFSCR SOVH SPEFSCR SOVH | ovh<br />

SPEFSCR SOV SPEFSCR SOV | ovl<br />

For each word element in the accumulator, corresponding<br />

word unsigned-integer elements in RA and RB are<br />

multiplied producing a 64-bit product. The least significant<br />

32 bits of each product are then added to the corresponding<br />

word in the accumulator saturating if<br />

overflow occurs, and the result is placed in RT and the<br />

accumulator.<br />

Special Registers Altered:<br />

ACC, OV, OVH, SOV, SOVH<br />

temp 0:63 (RA) 0:31 × ui (RB) 0:31<br />

temp 0:63 EXTZ((ACC) 0:31 ) - EXTZ(temp 32:63 )<br />

ovh temp 31<br />

RT 0:31 SATURATE(ovh, 0, 0x0000_0000, 0x0000_0000,<br />

temp 32:63 )<br />

temp 0:63 (RA) 32:63 × ui (RB) 32:63<br />

temp 0:63 EXTZ((ACC) 32:63 ) - EXTZ(temp 32:63 )<br />

ovl temp 31<br />

RT 32:63 SATURATE(ovl, 0, 0x0000_0000,<br />

0x0000_0000, temp 32:63 )<br />

ACC 0:63 (RT) 0:63<br />

SPEFSCR OVH ovh<br />

SPEFSCR OV ovl<br />

SPEFSCR SOVH SPEFSCR SOVH | ovh<br />

SPEFSCR SOV SPEFSCR SOV | ovl<br />

For each word element in the accumulator, corresponding<br />

word unsigned-integer elements in RA and RB are<br />

multiplied producing a 64-bit product. The least significant<br />

32 bits of each product are then subtracted from<br />

the corresponding word in the accumulator saturating if<br />

overflow occurs, and the result is placed in RT and the<br />

accumulator.<br />

Special Registers Altered:<br />

ACC, OV, OVH, SOV, SOVH<br />

Vector Multiply Word Signed, Modulo,<br />

Fractional<br />

EVX-form<br />

Vector Multiply Word Signed, Modulo,<br />

Fractional to Accumulator EVX-form<br />

evmwsmf<br />

RT,RA,RB<br />

evmwsmfa<br />

RT,RA,RB<br />

4 RT RA RB 1115<br />

0 6 11 16 21 31<br />

4 RT RA RB 1147<br />

0 6 11 16 21 31<br />

RT 0:63 (RA) 32:63 × sf (RB) 32:63<br />

The corresponding low word signed fractional elements<br />

in RA and RB are multiplied. The product is placed in<br />

RT.<br />

Special Registers Altered:<br />

None<br />

RT 0:63 (RA) 32:63 × sf (RB) 32:63<br />

ACC 0:63 (RT) 0:63<br />

The corresponding low word signed fractional elements<br />

in RA and RB are multiplied. The product is placed in<br />

RT and into the accumulator.<br />

Special Registers Altered:<br />

ACC<br />

Chapter 6. Signal Processing Engine (SPE)<br />

235

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