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Power ISA™ Version 2.03 - Power.org

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<strong>Version</strong> <strong>2.03</strong><br />

Extended Mnemonics:<br />

Extended mnemonics for Synchronize:<br />

Extended:<br />

Equivalent to:<br />

sync sync 0<br />

msync sync 0<br />

lwsync sync 1<br />

ptesync sync 2<br />

Except in the sync instruction description in this section,<br />

references to “sync” in Books I - III imply L=0<br />

unless otherwise stated or obvious from context; the<br />

appropriate extended mnemonics are used when other<br />

L values are intended.<br />

Programming Note<br />

Section 1.8 contains a detailed description of how<br />

to modify instructions such that a well-defined<br />

result is obtained.<br />

Programming Note<br />

sync serves as both a basic and an extended mnemonic.<br />

The Assembler will recognize a sync mnemonic<br />

with one operand as the basic form, and a<br />

sync mnemonic with no operand as the extended<br />

form. In the extended form the L operand is omitted<br />

and assumed to be 0.<br />

Programming Note<br />

The sync instruction can be used to ensure that all<br />

stores into a data structure, caused by Store<br />

instructions executed in a “critical section” of a program,<br />

will be performed with respect to another<br />

processor before the store that releases the lock is<br />

performed with respect to that processor; see<br />

Section B.2, “Lock Acquisition and Release, and<br />

Related Techniques” on page 379.<br />

The memory barrier created by a sync instruction<br />

with L=0 or L=1 does not order implicit storage<br />

accesses. The memory barrier created by a sync<br />

instruction with any L value does not order instruction<br />

fetches.<br />

(The memory barrier created by a sync instruction<br />

with L=0 – or L=2; see Book III – appears to<br />

order instruction fetches for instructions preceding<br />

the sync instruction with respect to data accesses<br />

caused by instructions following the sync instruction.<br />

However, this ordering is a consequence of<br />

the first “additional property” of sync with L=0, not<br />

a property of the memory barrier.)<br />

In order to obtain the best performance across the<br />

widest range of implementations, the programmer<br />

should use the sync instruction with L=1, or the<br />

eieio or mbar instruction, if any of these is<br />

sufficient for his needs; otherwise he should use<br />

sync with L=0. sync with L=2 should not be<br />

used by application programs.<br />

Programming Note<br />

The functions provided by sync with L=1 are a<br />

strict subset of those provided by sync with L=0.<br />

(The functions provided by sync with L=2 are a<br />

strict superset of those provided by sync with L=0;<br />

see Book III.)<br />

366<br />

<strong>Power</strong> ISA -- Book II

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