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<strong>Version</strong> <strong>2.03</strong><br />
464<br />
<strong>Power</strong> ISA -- Book III-S
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Power ISA™ Version 2.03 - Power.org
Power ISA™ Version 2.03 - Power.org
YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.
<strong>Version</strong> <strong>2.03</strong><br />
464<br />
<strong>Power</strong> ISA -- Book III-S
<strong>Version</strong> <strong>2.03</strong> 464 <strong>Power</strong> ISA -- Book III-S
<strong>Version</strong> <strong>2.03</strong> Chapter 9. External Control [Category: External Control] 9.1 External Access Register . . . . . . . 465 9.2 External Access Instructions. . . . . 465 The External Control facility permits a program to communicate with a special-purpose device. The facility consists of a Special Purpose Register, called EAR, and two instructions, called External Control In Word Indexed (eciwx) and External Control Out Word Indexed (ecowx). This facility must provide a means of synchronizing the devices with the processor to prevent the use of an address by the device when the translation that produced that address is being invalidated. 9.1 External Access Register This 32-bit Special Purpose Register controls access to the External Control facility and, for external control operations that are permitted, identifies the target device. 9.2 External Access Instructions The External Access instructions, External Control In Word Indexed (eciwx) and External Control Out Word Indexed (ecowx), are described in Book II. Additional information about them is given below. If attempt is made to execute either of these instructions when EAR E =0, a Data Storage interrupt occurs with bit 43 of the DSISR set to 1. The instructions are supported whenever MSR DR =1. If either instruction is executed when MSR DR =0 (real addressing mode), the results are boundedly undefined. E /// RID 32 33 58 63 Bit(s) Name Description 32 E Enable bit 58:63 RID Resource ID All other fields are reserved. Figure 43. External Access Register The EAR is a hypervisor resource; see Chapter 2. The high-order bits of the RID field that correspond to bits of the Resource ID beyond the width of the Resource ID supported by the implementation are treated as reserved bits. Programming Note The hypervisor can use the EAR to control which programs are allowed to execute External Access instructions, when they are allowed to do so, and which devices they are allowed to communicate with using these instructions. Chapter 9. External Control [Category: External Control] 465
® Power ISA Version 2.03 September
Version 2.03 Preface The roots of t
Version 2.03 Table of Contents Pref
Version 2.03 Chapter 5. Vector Proc
Version 2.03 D.8 Move To/From Speci
Version 2.03 5.7.1 32-Bit Mode . .
Version 2.03 4.6 Invalid Real Addre
Version 2.03 8.6 Debugger Notify Ha
Version 2.03 5.8 Fixed-Point Select
Version 2.03 Figures Preface ......
Version 2.03 40. MMU Control and St
Version 2.03 Book I: Power ISA User
Version 2.03 Chapter 1. Introductio
Version 2.03 GPR, FPR, or VR (e.g.
Version 2.03 SPR(x) Special Purpose
Version 2.03 An instruction in a ca
Version 2.03 CR 32 63 “Condition
Version 2.03 1.6.3 SC-FORM 0 6 11 1
Version 2.03 1.6.19 EVX-FORM 0 6 11
Version 2.03 SPR (11:20) Field used
Version 2.03 for each virtual page,
Version 2.03 beq done loop: cmplwi
Version 2.03 Chapter 2. Branch Proc
Version 2.03 or (RB) (unsigned comp
Version 2.03 Programming Note Many
Version 2.03 Branch I-form Branch C
Version 2.03 2.5 Condition Register
Version 2.03 2.6 System Call Instru
Version 2.03 Chapter 3. Fixed-Point
Version 2.03 3.2.3 Program Priority
Version 2.03 Load Byte and Zero D-f
Version 2.03 Load Halfword Algebrai
Version 2.03 3.3.2.1 64-bit Fixed-P
Version 2.03 3.3.3 Fixed-Point Stor
Version 2.03 Store Word D-form Stor
Version 2.03 3.3.4 Fixed-Point Load
Version 2.03 3.3.6 Fixed-Point Move
Version 2.03 Store String Word Imme
Version 2.03 3.3.8 Fixed-Point Arit
Version 2.03 Subtract From Immediat
Version 2.03 Add to Zero Extended X
Version 2.03 Divide Word XO-form di
Version 2.03 Divide Doubleword XO-f
Version 2.03 Compare Logical Immedi
Version 2.03 3.3.10.1 64-bit Fixed-
Version 2.03 OR Immediate Shifted D
Version 2.03 NOR X-form Equivalent
Version 2.03 3.3.12.1 64-bit Fixed-
Version 2.03 Rotate Left Word Immed
Version 2.03 3.3.13.1.1 64-bit Fixe
Version 2.03 Rotate Left Doubleword
Version 2.03 Shift Right Algebraic
Version 2.03 3.3.14 Move To/From Sy
Version 2.03 Move To Condition Regi
Version 2.03 3.3.14.1 Move To/From
Version 2.03 Chapter 4. Floating-Po
Version 2.03 the FPRs with no conve
Version 2.03 59 Floating-Point Zero
Version 2.03 due to the invalid ope
Version 2.03 Programming Note The F
Version 2.03 When an exception occu
Version 2.03 When Invalid Operation
Version 2.03 4.4.5 Inexact Exceptio
Version 2.03 4.5.2 Execution Model
Version 2.03 Load Floating-Point Si
Version 2.03 4.6.3 Floating-Point S
Version 2.03 Store Floating-Point D
Version 2.03 4.6.4 Floating-Point M
Version 2.03 Floating Multiply [Sin
Version 2.03 Floating Reciprocal Sq
Version 2.03 Floating Negative Mult
Version 2.03 Floating Convert To In
Version 2.03 Floating Round to Inte
Version 2.03 4.6.8 Floating-Point S
Version 2.03 Move To FPSCR Bit 0 X-
Version 2.03 Chapter 5. Vector Proc
Version 2.03 Quadword Word 0 Word 1
Version 2.03 halfword, or word resp
Version 2.03 5.5 Vector Integer Ope
Version 2.03 If an exception occurs
Version 2.03 5.7.2 Vector Load Inst
Version 2.03 5.7.3 Vector Store Ins
Version 2.03 5.7.4 Vector Alignment
Version 2.03 Vector Pack Signed Hal
Version 2.03 Vector Unpack High Pix
Version 2.03 5.8.2 Vector Merge Ins
Version 2.03 5.8.3 Vector Splat Ins
Version 2.03 5.8.6 Vector Shift Ins
Version 2.03 5.9 Vector Integer Ins
Version 2.03 Vector Add Unsigned By
Version 2.03 Vector Subtract Unsign
Version 2.03 5.9.1.3 Vector Integer
Version 2.03 5.9.1.4 Vector Integer
Version 2.03 Vector Multiply-Sum Si
Version 2.03 5.9.1.5 Vector Integer
Version 2.03 5.9.1.6 Vector Integer
Version 2.03 5.9.1.7 Vector Integer
Version 2.03 Vector Minimum Signed
Version 2.03 5.9.2 Vector Integer C
Version 2.03 Vector Compare Greater
Version 2.03 5.9.4 Vector Integer R
Version 2.03 Vector Shift Right Alg
Version 2.03 5.10 Vector Floating-P
Version 2.03 5.10.2 Vector Floating
Version 2.03 Vector Convert from Si
Version 2.03 5.10.4 Vector Floating
Version 2.03 5.10.5 Vector Floating
Version 2.03 5.11 Vector Status and
Version 2.03 Chapter 6. Signal Proc
Version 2.03 has occurred in the up
Version 2.03 If the exception is en
Version 2.03 6.3.7 SPE Instructions
Version 2.03 Vector Add Signed, Sat
Version 2.03 Vector Compare Greater
Version 2.03 Vector Divide Word Uns
Version 2.03 Vector Load Double int
Version 2.03 Vector Load Word into
Version 2.03 Vector Load Word into
Version 2.03 Vector Multiply Halfwo
Version 2.03 Vector Multiply Halfwo
Version 2.03 Vector Multiply Halfwo
Version 2.03 Vector Multiply Halfwo
Version 2.03 Vector Multiply Halfwo
Version 2.03 Vector Multiply Halfwo
Version 2.03 Vector Multiply Halfwo
Version 2.03 Vector Multiply Halfwo
Version 2.03 Initialize Accumulator
Version 2.03 Vector Multiply Word L
Version 2.03 Vector Multiply Word L
Version 2.03 Vector Multiply Word S
Version 2.03 Vector Multiply Word U
Version 2.03 Vector Rotate Left Wor
Version 2.03 Vector Shift Right Wor
Version 2.03 Vector Store Word of T
Version 2.03 Vector Subtract Unsign
Version 2.03 Chapter 7. Embedded Fl
Version 2.03 Denormalized numbers o
Version 2.03 7.3 Embedded Floating-
Version 2.03 Vector Floating-Point
Version 2.03 Vector Floating-Point
Version 2.03 Vector Convert Floatin
Version 2.03 7.3.3 SPE.Embedded Flo
Version 2.03 Floating-Point Single-
Version 2.03 Floating-Point Single-
Version 2.03 Convert Floating-Point
Version 2.03 Floating-Point Double-
Version 2.03 Floating-Point Double-
Version 2.03 Convert Floating-Point
Version 2.03 Convert Floating-Point
Version 2.03 7.4 Embedded Floating-
Version 2.03 Table 3: Embedded Floa
Version 2.03 Table 7: Embedded Floa
Version 2.03 Chapter 8. Legacy Move
Version 2.03 Chapter 9. Legacy Inte
Version 2.03 Multiply Accumulate Hi
Version 2.03 Multiply Accumulate Lo
Version 2.03 Multiply High Halfword
Version 2.03 Negative Multiply Accu
Version 2.03 Appendix A. Suggested
Version 2.03 If FPSCR RN = 0b01 the
Version 2.03 A.2 Floating-Point Con
Version 2.03 Large Operand: FPSCR F
Version 2.03 A.4 Floating-Point Rou
Version 2.03 Appendix B. Vector RTL
Version 2.03 Appendix C. Embedded F
Version 2.03 C.3 Convert from Doubl
Version 2.03 C.5 Convert to Single-
Version 2.03 Appendix D. Assembler
Version 2.03 D.2.3 Branch Mnemonics
Version 2.03 D.4 Subtract Mnemonics
Version 2.03 These codes are reflec
Version 2.03 D.7.2 Operations on Wo
Version 2.03 Load Address This mnem
Version 2.03 Appendix E. Programmin
Version 2.03 Multiple-precision shi
Version 2.03 E.2.5 Conversion from
Version 2.03 E.4 Vector Unaligned S
Version 2.03 Book II: Power ISA Vir
Version 2.03 Chapter 1. Storage Mod
Version 2.03 Each program can acces
Version 2.03 cause additional locat
Version 2.03 1.7 Shared Storage Thi
Version 2.03 Programming Note The f
Version 2.03 Programming Note Becau
Version 2.03 1.8.1 Concurrent Modif
Version 2.03 Chapter 2. Effect of O
Version 2.03 Chapter 3. Storage Con
Version 2.03 3.2.2 Data Cache Instr
Version 2.03 description assumes th
Version 2.03 Programming Note This
Version 2.03 Data Cache Block set t
Version 2.03 3.2.2.1 Obsolete Data
Version 2.03 Store Word Conditional
Version 2.03 3.3.3 Memory Barrier I
Version 2.03 Enforce In-order Execu
Version 2.03 Chapter 4. Time Base 4
Version 2.03 Programming Note Since
Version 2.03 Chapter 5. External Co
Version 2.03 Appendix A. Assembler
Version 2.03 Appendix B. Programmin
Version 2.03 B.2 Lock Acquisition a
Version 2.03 B.3 List Insertion Thi
Version 2.03 Book III-S: Power ISA
Version 2.03 Chapter 1. Introductio
Version 2.03 the execution of a Ve
Version 2.03 Chapter 2. Logical Par
Version 2.03 2.5 Logical Partition
Version 2.03 Chapter 3. Branch Proc
Version 2.03 3.3 Branch Processor I
Version 2.03 Chapter 4. Fixed-Point
Version 2.03 4.3.5 Software-use SPR
Version 2.03 4.4.2 OR Instruction o
Version 2.03 Move To Special Purpos
Version 2.03 Move To Machine State
Version 2.03 Chapter 5. Storage Con
Version 2.03 stream being executed)
Version 2.03 5.7.2.3 Storage Contro
Version 2.03 Load Floating-Point Do
Version 2.03 Load Vector by Externa
Version 2.03 Chapter 4. Storage Con
Version 2.03 4.6 Invalid Real Addre
Version 2.03 SX Supervisor State Ex
Version 2.03 MSR DS for data storag
Version 2.03 4.7.4 Storage Access C
Version 2.03 Programming Note This
Version 2.03 Accesses to the same s
Version 2.03 4.9.2 Cache Locking [C
Version 2.03 4.9.2.3 Cache Locking
Version 2.03 4.9.3 Synchronize Inst
Version 2.03 TLB Search Indexed X-f
Version 2.03 Chapter 5. Interrupts
Version 2.03 5.2.3 Critical Save/Re
Version 2.03 5.2.9 Exception Syndro
Version 2.03 5.2.11.1 Machine Check
Version 2.03 exception that generat
Version 2.03 Programming Note For i
Version 2.03 IVOR Interrupt Excepti
Version 2.03 5.6.3 Data Storage Int
Version 2.03 cessing system. Also,
Version 2.03 MSR CM MSR CM is set t
Version 2.03 CSRR0, CSRR1, MSR, and
Version 2.03 5.6.17 SPE/Embedded Fl
Version 2.03 5.6.21 Processor Doorb
Version 2.03 5.8 Interrupt Ordering
Version 2.03 5.8.2 Interrupt Order
Version 2.03 5.9.1.5 Exception Prio
Version 2.03 Chapter 6. Reset and I
Version 2.03 Chapter 7. Timer Facil
Version 2.03 7.3 Decrementer The De
Version 2.03 Bit(s) Description 32:
Version 2.03 Time-out. No exception
Version 2.03 Chapter 8. Debug Facil
Version 2.03 Programming Note There
Version 2.03 Later, if the debug ex
Version 2.03 whose direction will b
Version 2.03 8.4.10 Critical Interr
Version 2.03 34:35 Instruction Addr
Version 2.03 40:41 Data Address Com
Version 2.03 8.5.3 Instruction Addr
Version 2.03 Chapter 9. Processor C
Version 2.03 9.3 Processor Control
Version 2.03 Chapter 10. Synchroniz
Version 2.03 If an mtmsr, wrtee, or
Version 2.03 Appendix A. Implementa
Version 2.03 A.2.1.3 Instruction Ca
Version 2.03 Instruction Cache Read
Version 2.03 Appendix B. Assembler
Version 2.03 Appendix C. Guidelines
Version 2.03 Appendix D. Type FSL S
Version 2.03 52:63 Next Victim (NV)
Version 2.03 58 Default VLE Value (
Version 2.03 D.2.5 MMU Configuratio
Version 2.03 D.4.3 Invalidating TLB
Version 2.03 D.6 Type FSL MMU Instr
Version 2.03 TLB Synchronize XL-for
Version 2.03 Appendix E. Example Pe
Version 2.03 counter with an event
Version 2.03 111 Threshold field is
Version 2.03 E.5 Performance Monito
Version 2.03 Book VLE: Power ISA Op
Version 2.03 Chapter 1. Variable Le
Version 2.03 1.4.6 R-form (16-bit M
Version 2.03 UI (6:10 || 21:31, 11:
Version 2.03 Chapter 2. VLE Storage
Version 2.03 ESR MIF is set when an
Version 2.03 Chapter 3. VLE Compati
Version 2.03 Chapter 4. Branch Oper
Version 2.03 4.2 Branch Instruction
Version 2.03 Branch to Count Regist
Version 2.03 Return From Machine Ch
Version 2.03 4.4 Condition Register
Version 2.03 Chapter 5. Fixed-Point
Version 2.03 Load Halfword Algebrai
Version 2.03 5.2 Fixed-Point Store
Version 2.03 Store Word D-form Stor
Version 2.03 5.5 Fixed-Point Arithm
Version 2.03 Add Scaled Immediate C
Version 2.03 5.6 Fixed-Point Compar
Version 2.03 Compare Logical Scaled
Version 2.03 Compare Halfword Logic
Version 2.03 OR (two operand) Immed
Version 2.03 Extend Sign Byte Short
Version 2.03 5.10 Fixed-Point Rotat
Version 2.03 Shift Right Algebraic
Version 2.03 Chapter 6. Storage Con
Version 2.03 Chapter 7. Additional
Version 2.03 Appendix A. VLE Instru
Version 2.03 Form Mode Dep. 1 Priv
Version 2.03 Form Mode Dep. 1 Priv
Version 2.03 Form Mode Dep. 1 Priv
Version 2.03 Form Mode Dep. 1 Priv
Version 2.03 Form Mode Dep. 1 Priv
Version 2.03 Form Mode Dep. 1 Priv
Version 2.03 Form Mode Dep. 1 Priv
Version 2.03 Appendix B. VLE Instru
Version 2.03 Form Mode Dep. 1 Priv
Version 2.03 Form Mode Dep. 1 Priv
Version 2.03 Form Mode Dep. 1 Priv
Version 2.03 Form Mode Dep. 1 Priv
Version 2.03 Form Mode Dep. 1 Priv
Version 2.03 Form Mode Dep. 1 Priv
Version 2.03 Form Mode Dep. 1 Priv
Version 2.03 Appendices: Power ISA
Version 2.03 Appendix A. Incompatib
Version 2.03 In POWER bits 20:26
Version 2.03 privilege: mfsr and mf
Version 2.03 A.32 POWER2 Compatibil
Version 2.03 Appendix B. Platform S
Version 2.03 Appendix C. Complete S
Version 2.03 decimal SPR 1 Register
Version 2.03 Appendix D. Illegal In
Version 2.03 Appendix E. Reserved I
Version 2.03 Appendix F. Opcode Map
Version 2.03 Table 2: Extended opco
Version 2.03 Table 5 (Left-Center)
Version 2.03 Table 5 (Right) Extend
Version 2.03 Table 6 (Left-Center)
Version 2.03 Table 6 (Right) Extend
Version 2.03 Table 7. (Right) Exten
Version 2.03 Table 8. (Right) Exten
Version 2.03 761
Version 2.03 763 Table 13. (Right)
Version 2.03 765 Table 14. (Right)
Version 2.03 Appendix G. Power ISA
Version 2.03 Form Opcode Pri Ext Mo
Version 2.03 Form Opcode Pri Ext Mo
Version 2.03 Form Opcode Pri Ext Mo
Version 2.03 Form Opcode Pri Ext Mo
Version 2.03 Form Opcode Pri Ext Mo
Version 2.03 Form Opcode Pri Ext Mo
Version 2.03 Form Opcode Pri Ext Mo
Version 2.03 Appendix H. Power ISA
Version 2.03 Form Opcode Pri Ext Mo
Version 2.03 Form Opcode Pri Ext Mo
Version 2.03 Form Opcode Pri Ext Mo
Version 2.03 Form Opcode Pri Ext Mo
Version 2.03 Form Opcode Pri Ext Mo
Version 2.03 Form Opcode Pri Ext Mo
Version 2.03 Form Opcode Pri Ext Mo
Version 2.03 Appendix I. Power ISA
Version 2.03 Form Opcode Pri Ext Mo
Version 2.03 Form Opcode Pri Ext Mo
Version 2.03 Form Opcode Pri Ext Mo
Version 2.03 Form Opcode Pri Ext Mo
Version 2.03 Form Opcode Pri Ext Mo
Version 2.03 Form Opcode Pri Ext Mo
Version 2.03 Form Opcode Pri Ext Mo
Version 2.03 Mode Dependency and Pr
Version 2.03 Index A a bit 26 A-for
Version 2.03 F FE 25, 92 FEX 91 FE0
Version 2.03 instructions classes 1
Version 2.03 Machine Status Save Re
Version 2.03 See Logical Partitioni
Version 2.03 Last Page - End of Doc
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