Power ISA™ Version 2.03 - Power.org

Version 2.03
Store Vector by External Process ID
Indexed
X-form
stvepx VRS,RA,RB (LRU = 0)
31 VRS RA RB 807 0
0 6 11 16 21 31
if RA = 0 then b 0
else
b (RA)
EA b + (RB)
MEM(EA & 0xFFFF_FFFF_FFFF_FFF0, 16) (VRS)
Let the effective address (EA) be the sum (RA|0)+(RB).
The contents of VRS are stored into the quadword in
storage addressed by the result of EA ANDed with
0xFFFF_FFFF_FFFF_FFF0.
For stvepx, the normal translation mechanism is not
used. The contents of the EPSC register are used to
provide the context in which translation occurs. The following
substitutions are made for just the translation
and access control process:
EPSC EPR is used in place of MSR PR
EPSC EAS is used in place of MSR DS
EPSC EPID is used in place of all Process ID registers
This instruction is privileged.
An attempt to execute stvepx while MSR SPV =0 will
cause a Vector Unavailable interrupt.
Corequisite Categories:
Vector
Special Registers Altered:
None
Programming Note
This instruction behaves identically to a stvx
instruction except for using the EPSC register to
provide the translation context.
Store Vector by External Process ID
Indexed LRU
X-form
stvepxl VRS,RA,RB (LRU = 1)
31 VRS RA RB 775 0
0 6 11 16 21 31
if RA = 0 then b 0
else
b (RA)
EA b + (RB)
MEM(EA & 0xFFFF_FFFF_FFFF_FFF0, 16) (VRS)
mark_as_not_likely_to_be_needed_again_anytime_soon
(EA)
Let the effective address (EA) be the sum (RA|0)+(RB).
The contents of VRS are stored into the quadword in
storage addressed by the result of EA ANDed with
0xFFFF_FFFF_FFFF_FFF0.
The stvepxl instruction provides a hint that the quadword
addressed by EA will probably not be needed
again by the program in the near future.
For stvepxl, the normal translation mechanism is not
used. The contents of the EPSC register are used to
provide the context in which translation occurs. The following
substitutions are made for just the translation
and access control process:
EPSC EPR is used in place of MSR PR
EPSC EAS is used in place of MSR DS
EPSC EPID is used in place of all Process ID registers
This instruction is privileged.
An attempt to execute stvepxl while MSR SPV =0 will
cause a Vector Unavailable interrupt.
Corequisite Categories:
Vector
Special Registers Altered:
None
Programming Note
See the Programming Notes for the lvxl instruction
in Section 5.7.2 of Book I.
Programming Note
This instruction behaves identically to a stvxl
instruction except for using the EPSC register to
provide the translation context.
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Power ISA -- Book III-E