Power ISA™ Version 2.03 - Power.org

Version 2.03
Vector Divide Word Unsigned
EVX-form
Vector Equivalent
EVX-form
evdivwu
RT,RA,RB
eveqv
RT,RA,RB
4 RT RA RB 1223
0 6 11 16 21 31
4 RT RA RB 537
0 6 11 16 21 31
ddh (RA) 0:31
ddl (RA) 32:63
dvh (RB) 0:31
dvl (RB) 32:63
RT 0:31 ddh ÷ dvh
RT 32:63 ddl ÷ dvl
ovh 0
ovl 0
if (dvh = 0) then
RT 0:31 0xFFFFFFFF
ovh 1
if (dvl = 0) then
RT 32:63 0xFFFFFFFF
ovl 1
SPEFSCR OVH ovh
SPEFSCR OV ovl
SPEFSCR SOVH SPEFSCR SOVH | ovh
SPEFSCR SOV SPEFSCR SOV | ovl
The two dividends are the two elements of the contents
of RA. The two divisors are the two elements of the
contents of RB. Two 32-bit quotients are formed as a
result of the division on each of the high and low elements
and the quotients are placed into RT. Remainders
are not supplied. Operands and quotients are
interpreted as unsigned integers.
Special Registers Altered:
OV, OVH, SOV, SOVH
Programming Note
Note that any overflow indication is always set as a
side effect of this instruction. No form is defined
that disables the setting of the overflow bits. In
case of overflow, a saturated value is delivered into
the destination register.
RT 0:31 (RA) 0:31 ≡ (RB) 0:31
RT 32:63 (RA) 32:63 ≡ (RB) 32:63
The corresponding elements of RA and RB are XORed
bitwise, and the complemented results are placed in
RT.
Special Registers Altered:
None
Vector Extend Sign Byte
evextsb
RT,RA
RT 0:31 EXTS((RA) 24:31 )
RT 32:63 EXTS((RA) 56:63 )
EVX-form
The signs of the low-order byte in each of the elements
in RA are extended, and the results are placed in RT.
Special Registers Altered:
None
Vector Extend Sign Halfword
evextsh
4 RT RA /// 522
0 6 11 16 21 31
RT,RA
4 RT RA /// 523
EVX-form
0 6 11 16 21 31
RT 0:31 EXTS((RA) 16:31 )
RT 32:63 EXTS((RA) 48:63 )
The signs of the odd halfwords in each of the elements
in RA are extended, and the results are placed in RT.
Special Registers Altered:
None
Chapter 6. Signal Processing Engine (SPE)
207