Power ISA™ Version 2.03 - Power.org

Version 2.03
Vector Multiply Halfwords, Odd, Signed,
Saturate, Integer and Accumulate into
Words
EVX-form
evmhossiaaw RT,RA,RB
4 RT RA RB 1285
0 6 11 16 21 31
Vector Multiply Halfwords, Odd, Signed,
Saturate, Integer and Accumulate
Negative into Words
EVX-form
evmhossianw RT,RA,RB
4 RT RA RB 1413
0 6 11 16 21 31
temp 0:31 (RA) 16:31 × si (RB) 16:31
temp 0:63 EXTS((ACC) 0:31 ) + EXTS(temp 0:31 )
ovh (temp 31 ⊕ temp 32 )
RT 0:31 SATURATE(ovh, temp 31 , 0x8000_0000,
0x7FFF_FFFF, temp 32:63 )
temp 0:31 (RA) 48:63 × si (RB) 48:63
temp 0:63 EXTS((ACC) 32:63 ) + EXTS(temp 0:31 )
ovl (temp 31 ⊕ temp 32 )
RT 32:63 SATURATE(ovl, temp 31 , 0x8000_0000,
0x7FFF_FFFF, temp 32:63 )
ACC 0:63 (RT) 0:63
SPEFSCR OVH ovh
SPEFSCR OV ovl
SPEFSCR SOVH SPEFSCR SOVH | ovh
SPEFSCR SOV SPEFSCR SOV | ovl
The corresponding odd-numbered halfword
signed-integer elements in RA and RB are multiplied
producing a 32-bit product. Each 32-bit product is then
added to the corresponding word in the accumulator
saturating if overflow occurs, and the result is placed in
RT and the accumulator.
Special Registers Altered:
ACC, OV, OVH, SOV, SOVH
temp 0:31 (RA) 16:31 × si (RB) 16:31
temp 0:63 EXTS((ACC) 0:31 ) - EXTS(temp 0:31 )
ovh (temp 31 ⊕ temp 32 )
RT 0:31 SATURATE(ovh, temp 31 , 0x8000_0000,
0x7FFF_FFFF, temp 32:63 )
temp 0:31 (RA) 48:63 × si (RB) 48:63
temp 0:63 EXTS((ACC) 32:63 ) - EXTS(temp 0:31 )
ovl (temp 31 ⊕ temp 32 )
RT 32:63 SATURATE(ovl, temp 31 , 0x8000_0000,
0x7FFF_FFFF, temp 32:63 )
ACC 0:63 (RT) 0:63
SPEFSCR OVH ovh
SPEFSCR OV ovl
SPEFSCR SOVH SPEFSCR SOVH | ovh
SPEFSCR SOV SPEFSCR SOV | ovl
The corresponding odd-numbered halfword
signed-integer elements in RA and RB are multiplied
producing a 32-bit product. Each 32-bit product is then
subtracted from the corresponding word in the accumulator
saturating if overflow occurs, and the result is
placed in RT and the accumulator.
Special Registers Altered:
ACC, OV, OVH, SOV, SOVH
Vector Multiply Halfwords, Odd,
Vector Multiply Halfwords, Odd,
Unsigned, Modulo, Integer EVX-form Unsigned, Modulo, Integer to
Accumulator
EVX-form
evmhoumi RT,RA,RB
evmhoumia RT,RA,RB
4 RT RA RB 1036
0 6 11 16 21 31 4 RT RA RB 1068
0 6 11 16 21 31
RT 0:31 (RA) 16:31 × ui (RB) 16:31
RT 32:63 (RA) 48:63 × ui (RB) 48:63
The corresponding odd-numbered halfword
unsigned-integer elements in RA and RB are multiplied.
The two 32-bit products are placed into the corresponding
words of RT.
Special Registers Altered:
None
RT 0:31 (RA) 16:31 × ui (RB) 16:31
RT 32:63 (RA) 48:63 × ui (RB) 48:63
ACC 0:63 (RT) 0:63
The corresponding odd-numbered halfword
unsigned-integer elements in RA and RB are multiplied.
The two 32-bit products are placed into RT and
into the accumulator.
Special Registers Altered:
ACC
Chapter 6. Signal Processing Engine (SPE)
229