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59 Floating-Point Zero Divide Exception
Enable (ZE)
See Section 4.4.2, “Zero Divide Exception” on
page 101.
60 Floating-Point Inexact Exception Enable
(XE)
See Section 4.4.5, “Inexact Exception” on
page 103.
61 Floating-Point Non-IEEE Mode (NI)
Floating-point non-IEEE mode is optional. If
floating-point non-IEEE mode is not implemented,
this bit is treated as reserved, and the
remainder of the definition of this bit does not
apply.
If floating-point non-IEEE mode is implemented,
this bit has the following meaning.
0 The processor is not in floating-point
non-IEEE mode (i.e., all floating-point
operations conform to the IEEE standard).
1 The processor is in floating-point
non-IEEE mode.
When the processor is in floating-point
non-IEEE mode, the remaining FPSCR bits
may have meanings different from those given
in this document, and floating-point operations
need not conform to the IEEE standard. The
effects of executing a given floating-point
instruction with FPSCR NI =1, and any additional
requirements for using non-IEEE mode,
are implementation-dependent. The results of
executing a given instruction in non-IEEE
mode may vary between implementations,
and between different executions on the same
implementation.
Programming Note
When the processor is in floating-point
non-IEEE mode, the results of floating-point
operations may be approximate,
and performance for these operations
may be better, more predictable, or less
data-dependent than when the processor
is not in non-IEEE mode. For example, in
non-IEEE mode an implementation may
return 0 instead of a denormalized number,
and may return a large number
instead of an infinity.
62:63 Floating-Point Rounding Control (RN) See
Section 4.3.6, “Rounding” on page 97.
00 Round to Nearest
01 Round toward Zero
10 Round toward +Infinity
11 Round toward -Infinity
Result
Flags
Result Value Class
C < > = ?
1 0 0 0 1 Quiet NaN
0 1 0 0 1 - Infinity
0 1 0 0 0 - Normalized Number
1 1 0 0 0 - Denormalized Number
1 0 0 1 0 - Zero
0 0 0 1 0 + Zero
1 0 1 0 0 + Denormalized Number
0 0 1 0 0 + Normalized Number
0 0 1 0 1 + Infinity
Figure 45. Floating-Point Result Flags
4.3 Floating-Point Data
4.3.1 Data Format
This architecture defines the representation of a floating-point
value in two different binary fixed-length formats.
The format may be a 32-bit single format for a
single-precision value or a 64-bit double format for a
double-precision value. The single format may be used
for data in storage. The double format may be used for
data in storage and for data in floating-point registers.
The lengths of the exponent and the fraction fields differ
between these two formats. The structure of the single
and double formats is shown below.
S EXP FRACTION
32 33 41 63
Figure 46. Floating-point single format
S EXP FRACTION
0 1 12 63
Figure 47. Floating-point double format
Values in floating-point format are composed of three
fields:
S
sign bit
EXP exponent+bias
FRACTION fraction
Representation of numeric values in the floating-point
formats consists of a sign bit (S), a biased exponent
(EXP), and the fraction portion (FRACTION) of the significand.
The significand consists of a leading implied
bit concatenated on the right with the FRACTION. This
leading implied bit is 1 for normalized numbers and 0
for denormalized numbers and is located in the unit bit
position (i.e., the first bit to the left of the binary point).
Values representable within the two floating-point for-
Chapter 4. Floating-Point Processor [Category: Floating-Point]
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