Power ISA™ Version 2.03 - Power.org

Version 2.03
application program
A program that uses only the instructions and
resources described in Books I and II.
quadwords, doublewords, words, halfwords,
and bytes
128 bits, 64 bits, 32 bits, 16 bits, and 8 bits,
respectively.
positive
Means greater than zero.
negative
Means less than zero.
floating-point single format (or simply single
format)
Refers to the representation of a single-precision
binary floating-point value in a register or storage.
floating-point double format (or simply double
format)
Refers to the representation of a double-precision
binary floating-point value in a register or storage.
system library program
A component of the system software that can be
called by an application program using a Branch
instruction.
system service program
A component of the system software that can be
called by an application program using a System
Call instruction.
system trap handler
A component of the system software that receives
control when the conditions specified in a Trap
instruction are satisfied.
system error handler
A component of the system software that receives
control when an error occurs. The system error
handler includes a component for each of the various
kinds of error. These error-specific components
are referred to as the system alignment error
handler, the system data storage error handler,
etc.
latency
Refers to the interval from the time an instruction
begins execution until it produces a result that is
available for use by a subsequent instruction.
unavailable
Refers to a resource that cannot be used by the
program. For example, storage is unavailable if
access to it is denied. See Book III.
undefined value
May vary between implementations, and between
different executions on the same implementation,
and similarly for register contents, storage contents,
etc., that are specified as being undefined.
boundedly undefined
The results of executing a given instruction are
said to be boundedly undefined if they could have
been achieved by executing an arbitrary finite
sequence of instructions (none of which yields
boundedly undefined results) in the state the processor
was in before executing the given instruction.
Boundedly undefined results may include the
presentation of inconsistent state to the system
error handler as described in Section 1.8.1 of Book
II. Boundedly undefined results for a given instruction
may vary between implementations, and
between different executions on the same implementation.
“must”
If software violates a rule that is stated using the
word “must” (e.g., “this field must be set to 0”), the
results are boundedly undefined unless otherwise
stated.
sequential execution model
The model of program execution described in
Section 2.2, “Instruction Execution Order” on
page 23.
1.3.2 Notation
The following notation is used throughout the Power
ISA documents.
All numbers are decimal unless specified in some
special way.
- 0bnnnn means a number expressed in binary
format.
- 0xnnnn means a number expressed in hexadecimal
format.
Underscores may be used between digits.
RT, RA, R1, ... refer to General Purpose Registers.
FRT, FRA, FR1, ... refer to Floating-Point Registers.
VRT, VRA, VR1, ... refer to Vector Registers.
(x) means the contents of register x, where x is the
name of an instruction field. For example, (RA)
means the contents of register RA, and (FRA)
means the contents of register FRA, where RA and
FRA are instruction fields. Names such as LR and
CTR denote registers, not fields, so parentheses
are not used with them. Parentheses are also
omitted when register x is the register into which
the result of an operation is placed.
(RA|0) means the contents of register RA if the RA
field has the value 1-31, or the value 0 if the RA
field is 0.
Bits in registers, instructions, fields, and bit strings
are specified as follows. In the last three items
(definition of X p etc.), if X is a field that specifies a
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Power ISA -- Book I