Power ISA™ Version 2.03 - Power.org

Version 2.03
Floating Negative Multiply-Add [Single]
A-form
fnmadd FRT,FRA,FRC,FRB (Rc=0)
fnmadd. FRT,FRA,FRC,FRB (Rc=1)
63 FRT FRA FRB FRC 31 Rc
0 6 11 16 21 26 31
fnmadds FRT,FRA,FRC,FRB (Rc=0)
fnmadds. FRT,FRA,FRC,FRB (Rc=1)
59 FRT FRA FRB FRC 31 Rc
0 6 11 16 21 26 31
The operation
FRT - ( [(FRA)×(FRC)] + (FRB) )
is performed.
The floating-point operand in register FRA is multiplied
by the floating-point operand in register FRC. The
floating-point operand in register FRB is added to this
intermediate result.
If the most significant bit of the resultant significand is
not 1, the result is normalized. The result is rounded to
the target precision under control of the Floating-Point
Rounding Control field RN of the FPSCR, then negated
and placed into register FRT.
This instruction produces the same result as would be
obtained by using the Floating Multiply-Add instruction
and then negating the result, with the following exceptions.
QNaNs propagate with no effect on their “sign” bit.
QNaNs that are generated as the result of a disabled
Invalid Operation Exception have a “sign” bit
of 0.
SNaNs that are converted to QNaNs as the result
of a disabled Invalid Operation Exception retain
the “sign” bit of the SNaN.
FPSCR FPRF is set to the class and sign of the result,
except for Invalid Operation Exceptions when
FPSCR VE =1.
Special Registers Altered:
FPRF FR FI
FX OX UX XX
VXSNAN VXISI VXIMZ
CR1
(if Rc=1)
Floating Negative Multiply-Subtract
[Single]
A-form
fnmsub FRT,FRA,FRC,FRB (Rc=0)
fnmsub. FRT,FRA,FRC,FRB (Rc=1)
63 FRT FRA FRB FRC 30 Rc
0 6 11 16 21 26 31
fnmsubs FRT,FRA,FRC,FRB (Rc=0)
fnmsubs. FRT,FRA,FRC,FRB (Rc=1)
59 FRT FRA FRB FRC 30 Rc
0 6 11 16 21 26 31
The operation
FRT - ( [(FRA)×(FRC)] - (FRB) )
is performed.
The floating-point operand in register FRA is multiplied
by the floating-point operand in register FRC. The
floating-point operand in register FRB is subtracted
from this intermediate result.
If the most significant bit of the resultant significand is
not 1, the result is normalized. The result is rounded to
the target precision under control of the Floating-Point
Rounding Control field RN of the FPSCR, then negated
and placed into register FRT.
This instruction produces the same result as would be
obtained by using the Floating Multiply-Subtract
instruction and then negating the result, with the following
exceptions.
QNaNs propagate with no effect on their “sign” bit.
QNaNs that are generated as the result of a disabled
Invalid Operation Exception have a “sign” bit
of 0.
SNaNs that are converted to QNaNs as the result
of a disabled Invalid Operation Exception retain
the “sign” bit of the SNaN.
FPSCR FPRF is set to the class and sign of the result,
except for Invalid Operation Exceptions when
FPSCR VE =1.
Special Registers Altered:
FPRF FR FI
FX OX UX XX
VXSNAN VXISI VXIMZ
CR1
(if Rc=1)
Chapter 4. Floating-Point Processor [Category: Floating-Point]
119