Power ISA™ Version 2.03 - Power.org

Version 2.03
registers on the occurrence of a Data TLB Error Interrupt
or Instruction TLB Error interrupt.
When a Data or Instruction TLB Error interrupt (miss)
occurs, MAS0, MAS1, and MAS2 are automatically
updated using the defaults specified in MAS4 as well
as the AS and EPN values corresponding to the access
that caused the exception. MAS6 is updated to set
MAS6 SPID0 to the value of PID0 and MAS6 SAS to the
value of MSR DS or MSR IS depending on the type of
access that caused the error. In addition, if
MAS4 TLBSELD identifies a TLB array that supports NV
(Next Victim), MAS0 ESEL is loaded with a value that
hardware believes represents the best TLB entry to victimize
to create a new TLB entry and MAS0 NV is
updated with the TLB entry index of what hardware
believes to be the next victim. Thus MAS0 ESEL identifies
the current TLB entry to be replaced, and MAS0 NV
points to the next victim. When software writes the TLB
entry, the MAS0 NV field is written to the TLB array. The
algorithm used by the hardware to determine which
TLB entry should be targeted for replacement is implementation-dependent.
The automatic update of the MAS registers sets up all
the necessary fields for creating a new TLB entry with
the exception of RPN, the U0-U3 attribute bits, and the
permission bits. With the exception of the upper 32 bits
of RPN and the page attributes (should software desire
to specify changes from the default attributes), all the
remaining fields are located in MAS3, requiring only the
single MAS register manipulation by software before
writing the TLB entry.
For Instruction Storage interrupt (ISI) and Data Storage
interrupt (DSI) related exceptions, the MAS registers
are not updated. Software must explicitly search the
TLB to find the appropriate entry.
The update of MAS registers through TLB Replacement
Hardware Assist is summarized in Table 7.
exception was executing in 32-bit mode, then bits
0:31 of the EPN field in MAS2 will be set to 0.
Executing a tlbre instruction in 32-bit mode will set
bits 0:31 of the MAS2 EPN field to an undefined
value.
Programming Note
This allows a 32-bit OS to operate seamlessly on a
64-bit implementation and a 64-bit OS to easily
support 32-bit applications.
D.5 32-bit and 64-bit Specific
MMU Behavior
MMU behavior is largely unaffected by whether the processor
is in 32-bit computation mode (MSR CM =0) or
64-bit computation mode (MSR CM =1). The only differences
occur in the EPN field of the TLB entry and the
EPN field of MAS2. The differences are summarized
here.
Executing a tlbwe instruction in 32-bit mode will
set bits 0:31 of the TLB EPN field to 0, regardless
of the value of bits 0:31 of the EPN field in MAS2.
Updates to MAS registers via TLB Replacement
Hardware Assist (see Section D.4.5), update bits
0:51 of the EPN field regardless of the computation
mode of the processor at the time of the exception
or the interrupt computation mode in which the
interrupt is taken. If the instruction causing the
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Power ISA -- Book III-E