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Chapter 6. Storage Control Instructions
6.1 Storage Synchronization Instructions
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6.2 Cache Management Instructions . 690
6.3 Cache Locking Instructions . . . . . 690
6.4 TLB Management Instructions . . . 690
6.5 Instruction Alignment and Byte Ordering
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6.1 Storage Synchronization
Instructions
Instruction Synchronize
se_isync
C-form
The memory synchronization instructions implemented
by category VLE are identical in semantics to those
defined in Book II and Book III. The se_isync instruction
is defined by category VLE, but has the same
semantics as isync.
The Load and Reserve and Store Conditional instructions
from Book II, lwarx and stwcx. are available
while executing in VLE mode. The mnemonics, decoding,
and semantics for those instructions are identical
to those in Book II; see Section 3.3.2 of Book II for the
instruction definitions.
The Load and Reserve and Store Conditional instructions
from Book II, ldarx and stdcx. are available while
executing in VLE mode on 64-bit implementations. The
mnemonics, decoding, and semantics for those instructions
are identical to those in Book II; see Section 3.3.2
of Book II for the instruction definitions.
The Memory Barrier instructions from Book II, sync
(msync) and mbar are available while executing in
VLE mode. The mnemonics, decoding, and semantics
for those instructions are identical to those in Book II;
see Section 3.3.3 of Book II for the instruction definitions.
The wait instruction from Book II is available while executing
in VLE mode if the category Wait is implemented.
The mnemonics, decoding, and semantics for
wait are identical to those in Book II; see Section 3.3 of
Book II for the instruction definition.
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Executing an se_isync instruction ensures that all
instructions preceding the se_isync instruction have
completed before the se_isync instruction completes,
and that no subsequent instructions are initiated until
after the se_isync instruction completes. It also
ensures that all instruction cache block invalidations
caused by icbi instructions preceding the se_isync
instruction have been performed with respect to the
processor executing the se_isync instruction, and then
causes any prefetched instructions to be discarded.
Except as described in the preceding sentence, the
se_isync instruction may complete before storage
accesses associated with instructions preceding the
se_isync instruction have been performed. This
instruction is context synchronizing.
The se_isync instruction has identical semantics to the
Book II isync instruction, but has a different encoding.
Special Registers Altered:
None
Chapter 6. Storage Control Instructions
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