Power ISA™ Version 2.03 - Power.org

Version 2.03
Vector Multiply Halfwords, Odd,
Unsigned, Modulo, Integer and
Accumulate into Words EVX-form
Vector Multiply Halfwords, Odd,
Unsigned, Modulo, Integer and
Accumulate Negative into Words
EVX-form
evmhoumiaaw RT,RA,RB
evmhoumianw RT,RA,RB
4 RT RA RB 1292
0 6 11 16 21 31 4 RT RA RB 1420
0 6 11 16 21 31
temp 0:31 (RA) 16:31 × ui (RB) 16:31
RT 0:31 (ACC) 0:31 + temp 0:31
temp 0:31 (RA) 48:63 × ui (RB) 48:63
RT 32:63 (ACC) 32:63 + temp 0:31
ACC 0:63 (RT) 0:63
For each word element in the accumulator, the corresponding
odd-numbered halfword unsigned-integer
elements in RA and RB are multiplied. Each intermediate
product is added to the contents of the corresponding
accumulator word. The sums are placed into the
corresponding RT and accumulator words.
Special Registers Altered:
ACC
temp 0:31 (RA) 16:31 × ui (RB) 16:31
RT 0:31 (ACC) 0:31 - temp 0:31
temp 0:31 (RA) 48:63 × ui (RB) 48:63
RT 32:63 (ACC) 32:63 - temp 0:31
ACC 0:63 (RT) 0:63
For each word element in the accumulator, the corresponding
odd-numbered halfword unsigned-integer
elements in RA and RB are multiplied. Each intermediate
product is subtracted from the contents of the corresponding
accumulator word. The results are placed into
the corresponding RT and accumulator words.
Special Registers Altered:
ACC
Vector Multiply Halfwords, Odd,
Unsigned, Saturate, Integer and
Accumulate into Words EVX-form
Vector Multiply Halfwords, Odd,
Unsigned, Saturate, Integer and
Accumulate Negative into Words
EVX-form
evmhousiaaw RT,RA,RB
evmhousianw RT,RA,RB
4 RT RA RB 1284
0 6 11 16 21 31 4 RT RA RB 1412
0 6 11 16 21 31
temp 0:31 (RA) 16:31 × ui (RB) 16:31
temp 0:63 EXTZ((ACC) 0:31 ) + EXTZ(temp 0:31 )
ovh temp 31
RT 0:31 SATURATE(ovh, 0, 0xFFFF_FFFF, 0xFFFF_FFFF,
temp 32:63 )
temp 0:31 (RA) 48:63 × ui (RB) 48:63
temp 0:63 EXTZ((ACC) 32:63 ) + EXTZ(temp 0:31 )
ovl temp 31
RT 32:63 SATURATE(ovl, 0, 0xFFFF_FFFF,
0xFFFF_FFFF, temp 32:63 )
ACC 0:63 (RT) 0:63
SPEFSCR OVH ovh
SPEFSCR OV ovl
SPEFSCR SOVH SPEFSCR SOVH | ovh
SPEFSCR SOV SPEFSCR SOV | ovl
For each word element in the accumulator, corresponding
odd-numbered halfword unsigned-integer elements
in RA and RB are multiplied producing a 32-bit product.
Each 32-bit product is then added to the corresponding
word in the accumulator saturating if overflow occurs,
and the result is placed in RT and the accumulator.
Special Registers Altered:
ACC, OV, OVH, SOV, SOVH
temp 0:31 (RA) 16:31 × ui (RB) 16:31
temp 0:63 EXTZ((ACC) 0:31 ) - EXTZ(temp 0:31 )
ovh temp 31
RT 0:31 SATURATE(ovh, 0, 0x0000_0000, 0x0000_0000,
temp 32:63 )
temp 0:31 (RA) 48:63 × ui (RB) 48:63
temp 0:63 EXTZ((ACC) 32:63 ) - EXTZ(temp 0:31 )
ovl temp 31
RT 32:63 SATURATE(ovl, 0, 0x0000_0000,0x0000_0000,
temp 32:63 )
ACC 0:63 (RT) 0:63
SPEFSCR OVH ovh
SPEFSCR OV ovl
SPEFSCR SOVH SPEFSCR SOVH | ovh
SPEFSCR SOV SPEFSCR SOV | ovl
For each word element in the accumulator, corresponding
odd-numbered halfword unsigned-integer elements
in RA and RB are multiplied producing a 32-bit product.
Each 32-bit product is then subtracted from the corresponding
word in the accumulator saturating if overflow
occurs, and the result is placed in RT and the accumulator.
Special Registers Altered:
ACC, OV, OVH, SOV, SOVH
230
Power ISA -- Book I