of Microprocessors

MICROPROCESSORS 153
mabIe waveforms using simplified direct synthesis techniques. Many of these
applications will be detailed in later chapters.
The 6502 requires a single +5-V power supply, making it directly
compatible with TTL logic systems. A 16-bit address bus, 8-bit bidirectional
data bus, and numerous control signals are provided. Incredibly, there
are three unused pins on the package! The on-chip clock oscillator/driver
requires only a TTL inverter, a crystal (or R-C network), and a few passive
components to generate a two-phase nonoverlapping clock. Although the
standard frequency is only 1.0 MHz, a complete machine cycle is executed in
just one clock cycle.
According to the manufacturer's literature, there are no fewer than nine
different package and pin configurations of the basic 6502. Two of these are
the typical 40-lead dual-in-line package with all features available and the
other seven are smaller and cheaper 28-lead packages with different mixes of
omitted functions and intended for small configurations. The primary difference
between the two 40-lead versions is that the 6502 has a built-in clock
oscillator and driver, whereas the 6512 requires an external two-phase clock
oscillator and driver. The advantage of an external clock is that timing and
waveshapes can be precisely controlled, although the oscillator pins of 6502
can also be externally driven. Thus, the 6502 will be the model for further
discussion.
Bus Structure and Timing
Figure 5-1 shows a 6502 read cycle that is about as simple as one can
get. The I-J.Lsec machine cycle is divided into Phase 1, which is the first 500
nsec, and Phase 2, which is the last 500 nsec. Actually, when using the onchip
oscillator, the cycle may not be split exactly 50-50, but the signal
relationships are still valid. During Phase 1, the address bus and read/write
line settle to valid indications, and near the end of Phase 2 the microprocessor
reads the data bus. Static read-only devices can actually be
connected to the address and data buses without any other control signals at
all; if they see their address, they drive their data. Approximately 600 nsec is
allowed for memory access, although typically greater than 850 nsec can be
tolerated before malfunction.
I CLOCK CYCLE = I }J sec I
CLOCK ~~;g I ~'''' ~~
.,,"'~."'~ """ . -
READ/WRITE _ _ ~
DATA IN
1. 600 I 100
1?JZ??ZIZ?ZV7~~
Fig. 5-1. 6502 read cycle timing