of Microprocessors

DIGITAL HARDWARE
615
TO MULTIPLEXED
PHASE AOOE\
FREQUENCY
CONTROL IN
FREQUENCY
GENERATOR
ACCUMULATOR
elK
MAJOR CYCLE
RATE 62.5 kHz
Fig. 17-17. Harmonic-frequency generator
MINOR CYCLE
RATE 4 MHz
and the two accumulators are therefore actual registers rather than memories.
In operation, the frequency-generation accumulatOr is clocked at the 62.5­
kHz major cycle rate, while the indexing accumulator is clocked at the
4-MHz minor cycle rate. Note that the indexing accumulator must be
cleared at the beginning of every major cycle for proper operation.
Amplitude Multiplier
The amplitude multiplier is much more difficult to eliminate so let's
see what is involved in hardware multiplication. There are a multitude of
hardware multiplication techniques that would require an entire chapter to
describe in detail. There are, however, basically two ways of multiplying in
hardware. The first is the serial shift and add algorithm or serial multiplication.
When an M-bit multiplier is being multiplied by an N-bit multiplicand,
the basic approach is to examine the M bits one bit at a time and
based on the result either add the multiplicand to a product accumulator
followed by a shift or just do the shift (either the accumulator can move right
or the multiplicand can move left). This approach is economical of hardware
requiring just an N-bit adder, an M + N-bit shift register, and an N-bit
latch but is slow, since M clock cycles are necessary to compute the product.
With Schottky TTL logic, shift and add can be done at about a 20-MHz rate,
which means that a 10 X 10 multiplication requires 500 nsee to perform, too
slow for the Fourier series generator as currently specified, although possibly
adequate for a 32-harmonic implementation.
The second approach is called parallel multiplication. Essentially, a large
number of adders and gates is combined to form a massive combinational
logic network that acceprs the factors as static inputs and eventually produces
the product output after the logic states have stabilized. For short word
lengths, it may even be practical to use a ROM as a multiplication table.
Besides much higher speed, the parallel multiplier is much easier to use,
since no clocks or timing signals are necessary. Settling time from when
operands are applied to when the result is stable is in the 150-nsec range for
lO-bit operands and a 20-bit product.