of Microprocessors

DIGITAL HARDWARE 609
between the 4116s and the DAC is required. Almost any edge-triggered
latch can be used for the holding registers but the type 74175 will be
specified because of its low cost and ready availability. Figure 17-13 shows a
block diagram of the complete multiplexed oscillator. Excluding the timing
generator and interface to the control computer, the total digital IC package
count is approximately 40.
Timing
Figure 17-14 shows a timing diagram for the events that take place
during one minor clock cycle. The only difference from one minor cycle to the
next is the content of the minor cycle counter, which addresses the various
memories involved. Each minor clock cycle consists of two subcycles that are
termed internal and external subcycles. During the first subcycle, the required
internal oscillator calculations are performed. The second subcycle is available
to the external control computer for writing in new frequency control
words or new waveforms if it so desires. Each subcycle is further divided into
four "phases," each 125 nsec in duration. These phases are used to sequence
the various events that take place. All of the necessary timing signals (except
CAS, which utilizes a 30-nsec delay element) can be generated by a 3-bit
counter driven by an 8-MHz crystal-controlled clock.
At the beginning of a minor cycle, which is also the beginning of an
internal subcycle, the minor cycle counter is incremented, which causes an
address change to the frequency control memory and the accumulator memory.
Since these are bipolar memories, the newly addressed contents emerge
about 50 nsec later. The adder, which sees a stable input about midway
through Phase 0, produces a stable output by the middle of Phase 1. At the
beginning of Phase 2, the adder output is latched in the adder holding
register and during Phase 3 the sum is written back into the accumulator
memory. While all of this is going on, the previous contents of the accumulator
memory are used to address the waveform memory in conjunction
with 4 bits from the minor cycle counter, which identifies which stored
waveform to use. The address selector switches between low 7-bit mode and
high 7-bit mode as required by the 4116s at the beginning of Phase 2. The
RAS spans Phases 1 to 3 while the CAS spans Phases 2 and 3 but with a 30­
nsec turn-on delay to allow address switching to complete. At the end of
Phase 3, data from the waveform memory is available and is latched into the
DAC register.
The DAC is allowed to settle during the second subcycle and the
appropriate SAH channel is updated during the first half of the next minor
cycle. Thus, SAH channel I will actually contain the signal from oscillator
1-1 which is corrected simply by relabeling the analog outputs.
This time skew from one minor cycle to the next is an example of
pipelining, which is a very powerful logic throughput enhancement technique.
It is applicable whenever a repetitive sequence of operations is to be