of Microprocessors

164 MUSICAL ApPLICATIONS OF MICROPROCESSORS
Enable, which is equivalent to the 6502's Phase 2. The frequency of this
signal is one-tenth the clock frequency and has a 60% low, 40% high duty
cycle. Any normal 68000 bus cycle can be converted into a synchronous 6800
cycle by driving the Valid Peripheral Address (VPA) line low before the
beginning of State 4. This would normally be done by a decoder recognizing
the address of an I/O chip on the address lines. The 68000 will then wait
until Enable goes low, drive Valid Memory Address low, and then transfer
data when Enable goes high and low again. Since Enable is a uniform
frequency rectangular wave and 68000 bus cycles can start at any time, the
amount of time required to execute a 6800-compatible cycle can vary from 10
clocks to 18 clocks. One could in fact make all bus cycles 6800-compatible
by grounding the VPA line, but then system speed would be less than half of
its potential.
Severa] other bus control signals are available for more complex
systems. One of these is Bus Error, which will abort a bus cycle in progress
and generate an interrupt if activated. In a small system, its main use is to
flag attempted access of nonexistent memory as an error condition and return
to the operating system. In a large system using virtual memory, this signal
would come from the memory manager and would indicate that the area of
memory just addressed is on disk and needs to be swapped in. In such cases,
bus cycles can actually be retried by proper use of the Halt signal. A simple
system would just tie Halt and Reset together and use the result as the system
reset signal.
Three signals are used for direct memory access (DMA) applications.
These are Bus Request, Bus Grant, and Bus Grant Acknowledge. They
operate in a complex two-phase handshake sequence that will not be detailed
here. The 68000 is quite efficient in releasing the bus for DMA with as little
as one clock cycle of overhead involved. As is traditional with microprocessors,
once the 68000 has released control of the bus (which includes
data, adddress, and most of the controls), it is the responsibility of the DMA
device to generate all of the timing signals needed for data transfers.
Interrupts
All large computer systems have elaborate interrupt structures and the
68000 is no exception. Interrupts, which are called exceptions by Motorola,
can come from a variety of internal sources such as zero divide, external
hardware errors such as Bus Error, and from I/O devices. Every possible
interrupt source is assigned to a two-word (4-byte) vector in memory. These
vectors are stored at fixed addresses in memory starting at location zero and
extending up to 1023 for 255 possible interrupt sources. A summary of these
vectors is shown in Table 5-2. Each vectot, except number zero, is simply
the address of the interrupt service subroutine.
When an interrupt occurs, the processor status and a return address are
pushed onto the supervisor stack. Next, the corresponding vector is read to