of Microprocessors

MICROPROCESSORS 157
A close examination of a detailed instruction set listing immediately
reveals that no instruction is legal in all of these modes and that most can use
half or fewer of them. In particular, instructions using one index register for
an operand cannot use the same register in forming rhe address of the other
operand. Also, the unqualified indirect mode would be very useful generally,
but the same effect can be achieved with either of the other indirect forms if
the index register contains zero. 5 Other than these, the selection seems to be
well thought out, since the need for an unavailable combination is not
frequent. Note that the base page must be used to perform variable addressing
of any possible memory location; the indexed modes only have a range of 256
bytes due to the 8-bit size of the index registers.
A full instruction set listing is shown in Table 5-1 along with the
allowable addressing modes and execution time. One unique feature is that
shift and rotate instructions can work directly in memory and with indexed
addressing to boot! Note that the condition codes are set even when something
is merely loaded. Both the LSI-II style bit test and compare any
register instructions are also included, although the immediate form of bit
test is mysteriously absent. 5
There are some weak points too. For example, the arithmetic instructions
always include the carry in the calculation. For the more common
single-byte or subtract, it is necessary to first clear or set the carry flag,
respectively (if its current state is unknown). Conditional branches are
limited to true and complement testing of individual condition flags,
although the inclusion of an overflow indicator makes it easy to simulate all
of the combination forms also. One perennial headache is that index registers
must pass through the accumulator on the way to or from the stack. 5
Interfacing Tricks
Although not obvious from the foregoing description, the 6502 lends
itself well to individual bit control functions. For individual testing of
external conditions such as key closures, a standard digital multiplexor can
be connected ro respond to a range of addresses and gate the addressed input
onto the most significant bit of the data bus. A shift or rotate memory left
instruction can then copy the addressed condition into the carry flag for
testing without disturbing any of the registers. Inexpensive addressable
latches can be used for individual control of output bits, again without
disturbing any registers. If the addressable latches are wired to respond to a
group of addresses and take their data from the least significant bit of the
data bus, then a shift memory left will clear the addressed bit and a shift
5 The CMOS 6502 mentioned earlier does have an unindexed indirect addressing mode
added as well as several new instructions including bit tesr immediate and direct push
and pop of the index registers.