of Microprocessors

MICROPROCESSORS 161
8 MHz CLOCK
FUNCTION CODE
ADDRESS BUS
AODRESS STROBE
READ/WRITE
UDS, LOS
DTACK
DATA BUS
ACCESS TIM E =
290 nsec II
20
Fig. 5-3. Motorola 68000 read cycle (8-MHz operation)
Besides address and data strobe lines, the 68000 has three additional
lines that specify a function code. The function code acts like an address
modifier and identifies where the associated address came from as a 3-bit
code. Five of the possible combinations are used as follows: 001, user data;
010, user program; 101, supervisor data; HO, supervisor program; and 111,
interrupt acknowledge. In complex 68000-based systems, distinction between
operating system and user programs and also between program code
and data can be implemented using the function codes. In simpler singleuser
implementations, the function code is normally used only to identify
interrupt acknowledge bus cycles.
Virtually all normal 68000 program execution involves just two kinds
of bus cycles: a read cycle and a write cycle. Each of these requires jOur clock
cycles to execute (assuming no wait states); thus, the maximum bus cycle rate
is 2 MHz with the standard 8-MHz clock frequency. In addition to read and
write, there is a very rarely used read-modify-write cycle, a "68000­
compatible" cycle, and an interrupt acknowledge cycle.
Figure 5-3 shows a simplified 68000 read cycle. Each half-cycle of the
clock is given a "state number" of 0 through 7. The bus cycle begins with
State 0, during which the three/unction code lines are updated. Next, during
State 1, the address lines are activated with the correct address. Note that the
address lines are disabled and float between bus cycles, a feature that requires
careful address decoder design and can be confusing when address signals are
examined on an oscilloscope. After this addressing setup, the cycle proper
starts in State 2 when Address Strobe is asserted. For read cycles, the Read/
Write line remains high to specify a read. Also during State 2, the Lower
Data Strobe and Upper Data Strobe lines are driven low according to the type
of data transfer and remain along with Address Strobe until the end of the
cycle in State 7.