of Microprocessors

MICROPROCESSORS 173
and is set the same as Carryon arithmetic instructions but is not affected by
moves. The Extend bit is used instead of carry by the multiple-precision
instructions Add Extended and Subtract Extended. Conditional branch
instructions have a 4-bit field that is coded for useful combinations of the
condition codes. For example, the "greater than" jump condition is
determined by a complex logical combination of the Negative, Zero, and
Overflow bits such that it works even after comparing two signed numbers
that were large enough to cause overflow when subtracted in the comparison
process. Explicit branch conditions are available for all seven possible
relations between two operands, both signed and unsigned, plus an always
true and an always false condition to make a total of 16. The conditional
branch instruction itself can test for a condition and jump up to 126 bytes
away in a one-word instruction. A two-word format can jump up to 32K
bytes away while an unconditional jump instruction can use any addressing
mode to jump anywhere.
Other unusual or specialized instructions include test any bit by bit
number in either a register or memory and optionally set, clear, or flip it.
The bit number itself can either be specified in the instruction or in a data
register. Check is a single word instruction that simultaneously compares a
data register with zero and a value specified using any addressing mode. If
the register content is out of bounds, an interrupt is generated. This
instruction can be liberally sprinkled in sensitive code without significantly
increasing its space or time requirements. Another time-saver is the
Decrement and Branch instruction. As usual, it will decrement the content
of a register and simultaneously branch if the result is not yet negative.
However, it also tests a specified branch condition and will not branch if it is
met. Thus, there are two possible exits from a loop constructed using this
instruction. Link and Unlink instructions are used to conveniently reserve
space on the stack when a subroutine is entered and then freeing it upon
return. Load-Effective Address simply performs an addressing mode calculation
and puts the result into a specified address register or it can be pushed
onto the stack.
Speed
Computing the exact execution time of a particular 68000 instruction
is difficult because the effect of each addressing mode for both the source and
destination operands as well as the size specification must be considered. In
general, however, all of the simple instructions require time equal to the sum
of their memory cycles plus perhaps two to four more clock cycles for internal
computation. Shifts require two clock cycles per position shifted. Multiply
requires approximately 70 clocks, whereas divide needs 150, which translates
into 9 and 19 /-Lsec, respectively, at 8 MHz. Interrupt response takes about 44
clocks, which, when added to the longest possible instruction (a divide),