of Microprocessors

MUSIC SYNTHESIS SOFTWARE 655
0069 1041
0070 1041 DOUBLE SHIFT RIGHT UNSIGNED
0071 1041 46BO DSHR LSR ACCH SHIFT HIGH BYTE RIGHT AND PUT UNDERFLOW
0072 1043 BIT IN CARRY FLAG
0073 1043 66Bl ROR ACCl SHIFT LOW BYTE RIGHT BRINGING IN
0074 1045 UNDERFLOW BIT
0075 1045 60 RTS RETURN
0076 1046
0077 1046 DOUBLE SHIFT RIGHT SIGNED
0078 1046 A5BO DSHRS LOA ACCH FIRST COPY THE SIGN BIT INTO THE CARRY
0079 1048 2A ROL A FLAG
0080 1049 66BO ROR ACCH THEN SHIFT HIGH BYTE RIGHT BRINGING IN
0081 104B 66Bl ROR ACCL COPY OF SIGN BIT AND CONTINUE AS ABOVE
0082 1040 60 RTS RETURN
0083 104E
0084 104E UNSIGNED 8X8 MULTIPLY
0085 I04E ENTER WITH MULTIPLICAND IN ACCUMULATOR
0086 104E ENTER WITH MULTIPLIER IN ACCl
0087 I04E EXIT WITH DOUBLE LENGTH PRODUCT IN ACCH
0088 104E AND ACCL
0089 104E 8582 UMULT STA TEMPI SAVE MULTIPLICAND
0090 1050 A900 UMULTO LDA #0 ZERO UPPER PRODUCT
0091 1052 85BO STA ACCH
0092 1054 A009 LOY #9 SET CYCLE COUNT
0093 1056 18 CLC INITIALLY CLEAR CARRY
0094 1057 66BO UMULTI ROR ACCH SHIFT PSEUDO ACCUMULATOR RIGHT 'BRINGING
0095 1059 66Bl ROR ACCL IN ANY OVERFLOW FROM PREVIOUS ADD AND
0096 105B SH IFTI NG OUT NEXT MULTIPLIER BIT
0097 105B 88 DEY DECREMENT CYCLE COUNT AND
0098 105C FOOC BEQ MULTRT RETURN WHEN DONE
0099 lOSE 90F7 BCC UMUlTI SKIP ADDITION IF MULTIPLIER BIT WAS ZERO
0100 1060 A5BD LOA ACCH ADD SAVED MULTIPLICAND TO UPPER BYTE
0101 1062 18 CLC OF PSEUDO ACCUMULATOR
0102 1063 65B2 ADC TEMPI BEING CAREFUL TO PRESERVE ANY POSSIBLE
0103 1065 85BO STA ACCH CARRY OUT
0104 1067 4C5710 JMP UMULTI GO SHIFT PSEUDO ACCUMULATOR
0105 106A 60 MULTRT RTS
0106 106B
0107 106B UNSIGNED 16/8 DIVIDE
0108 106B ENTER WITH 16 BIT DIVIDEND IN ACCH,ACCL
0109 106B ENTER WITH DIVISOR IN REGISTER·A
0110 106B RETURN WITH QUOTIENT IN ACCL
0111 106B RETURN WITH REMAINOER IN ACCH
0112 106B DIVISOR MUST BE LARGER THAN ACCH TO
0113 106B AVOID OVERFLOW
0114 106B 85B2 UDIV STA TEMPI SAVE DIVISOR
0115 1060 A008 LOY #8 SET CYCLE COUNT
0116 106F 06Bl ASL ACCl SHIFT DIVIDEND LOW
0117 1071 26BO UOIVI ROL ACCH SHIFT DIVIDEND HIGH
0118 1073 800B 8CS UDIV2 JUMP IF A 1 SHIFTED OUT OF DIVIDEND
0119 1075 A5BO LOA ACCH SUBTRACT DIVISOR FROM ACCH
0120 1077 38 SEC
0121 1078 E5B2 SBC TEMPI
0122 107A 9010 BCC UDIV4 JUMP TO SHIFT AND COUNT IF UNDERFLOW IS
0123 107C IMMENIENT, CARRY IS OUOTIENT BIT
0124 107C 85BO STA ACCH STORE DIFFERENCE IF NO UNDERFLOW, CARRY
0125 107E FLAG IS OUOTIENT BIT
0126 107E BOOC BCS UDIV4 GO TO SHIFT AND COUNT
0127 1080 A5BO UDIV2 LOA ACCH SUBTRACT DIVISOR FROM ACCH
0128 1082 E5B2 SBC TEMPI
0129 1084 BOOS BCS UDIV3 SKIP IF UNDERFLOW IMMENIENT
0130 1086 85BO STA ACCH STORE DIFFERENCE IF NO UNDERFLOW
0131 1088 38 SEC OUOTIENT BIT IS A ONE
0132 1089 BOOI BCS UDIV4 GO TO SHIFT AND COUNT
Fig. 18-3. Signal-processing math package for the 6502