of Microprocessors

MICROPROCESSORS 163
conjunction with read/write being low. All signals remain stable until State 7
when the address and data strobes are removed. Address and data themselves
remain for one additional half-clock. Since valid data and address completely
overlaps read/write and the data strobes, there is no problem in using
transparent latches for output registers as there is in the 6502.
The read-modify-write cycle is shown in Figure 5-5. Most highperformance
minicomputers and mainframes use this type of cycle, which is
shorter than separate read and write cycles because the address is sent out only
once, to speed up certain instructions such as "increment memory." In the
68000, it is actually longer (10 clock cycles instead of 4 + 4) and used only
for interprocessor communication in a multiprocessor shared-memory system.
The idea is to link the testing (read) and setting (write) phases of
memory flag manipulation such that no other processor can test or change
that same flag between the two phases. Only one 68000 instruction, called
appropriately enough Test And Set, uses the read-modify-write cycle. Its
distinguishing feature is that Address Strobe remains active during both the
read and write halves of the cycle, which should prevent the bus arbitrator in
a multiprocessor system from giving control to another processor between the
halves. Since the Test And Set instruction does very little (other instructions
are much more useful for single-processor flag manipulation), its use can be
avoided and this type of bus cycle ignored in a simple system design.
Most of the time, 68000 bus cycles are executed back-to-back with no
dead time between State 7 of the previous cycle and State 0 of the next cycle.
This is due in part to pipelined internal operation in which the next
instruction is often read from memory while the previous one is still
executing. There can, however, be any number of idle clock cycles between
bus cycles, which causes problems when interfacing to I/O chips designed for
the 6800 (Motorola's original 8-bit microprocessor) and the 6502, which
require uniformly spaced bus cycles. The 68000 thus offers a "6800- (6502)
compatible bus cycle" option. At all times while power is applied and the
clock is running, the 68000 will generate a uniform rectangular wave called
B MHz CLOCK
----{C===================:::Jf-----
FUNCTION CODE :::x _
ADDRESS BUS
ADDRESS STROBE ~'-
-----JI
READI WRITE
UDS, LOS
DTACK
DATA BUS
ZJ ,'--- L.l./7777Z72:...::...::..:.~
~'- --'I ''-__--'1
~~~ W0/ff$ffiW&&'iWA I//l/ll/ffi
-----------(.....::.r- ~"},,~R~EA~D~DA~TA~
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