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DIGITAL HARDWARE 591<br />

Lsa<br />

I<br />

N+I DIVISOR INPUT<br />

I<br />

1 1<br />

MSS<br />

~--<br />

CEP [A IS IC ID<br />

..-- CEP IA IS IC [D<br />

LCEP IA<br />

IS f C fO<br />

CET<br />

CET<br />

r-- CET<br />

4:J LO 74161 TC- Lc LO 74161 TCU~ LD 74161 TC -<br />

a CLR c CLR c CLR<br />

CLK QA Qa Qc QD j CLK QA Qs Qc QD<br />

rClK QA Qs Qc QD<br />

MASTER<br />

CLOCK<br />

NOTE.<br />

ALL UNUSED INPUTS TIED TO<br />

A SOURCE OF LOGICAL ONE<br />

DIVIDED<br />

'------ FREQUENCY<br />

OUTPUT<br />

(NARROW PULSE)<br />

Fig. 17-1. Simple, high-speed divide-by-N counter<br />

The master clock may be as high as 15 MHz 00-40 MHz if "S" or "F"<br />

series TTL logic is used), and the output frequency consists <strong>of</strong> pulses with a<br />

length <strong>of</strong> one clock period. N may be changed at almost any time, but if it is<br />

changed within 10 nsec <strong>of</strong> the end <strong>of</strong> an output pulse, an incorrect value may<br />

be loaded into the counters and cause a momentary glitch (click) in the<br />

output frequency.<br />

The assumption behind the divide-by-N approach is that, if the clock<br />

frequency is high enough, the frequency increment between adjacent values<br />

<strong>of</strong> N will be small enough to be inaudible. Let's determine how high the<br />

master clock must be to get a resolution <strong>of</strong> 5 cents (1/20 <strong>of</strong> a semitone or<br />

0.3%) throughout the audio range. Taking the low end first, we seek a clock<br />

frequency, F, such that FIN=20.0 and FI(N-1)=20.06, where N is the<br />

division factor for a 20-Hz output. Using the standard procedure for solving<br />

simultaneous equations, F and N are found to be 6.68 kHz and 334, respectively.<br />

Solving the same equations at the upper end <strong>of</strong> the audio range gives<br />

an F <strong>of</strong> 6.68 MHz and N the same as before.<br />

Since the clock frequency must remain fixed, we are forced to use the<br />

6.68 MHz value <strong>of</strong> F, since using lower values will not provide the required<br />

amount <strong>of</strong> resolution at high frequencies. Thus, with a master clock <strong>of</strong> 6.68<br />

MHz, the division ratio varies from 334 for a 20-kHz output to 334,000 for<br />

a 20-Hz output. The counter circuit in Fig. 17-1 will therefore require 20<br />

bits or five 4-bit counters, which could then provide frequencies as low as 6.4<br />

Hz. While the resolution at high frequencies. barely meets specification, the<br />

resolution at low frequencies is 1,000 times better than required. Note that<br />

the high-frequency resolution can only be improved by a factor <strong>of</strong> two before<br />

counter speed limitations become a factor. Clear!y, the divide-by-N method<br />

<strong>of</strong> frequency generation performs best when generating low frequencies.<br />

One advantage <strong>of</strong> the divide-by-N method is that the output frequency<br />

is pure, that is, there is no jitter in the period other than that <strong>of</strong> the master

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