of Microprocessors

DIGITAL HARDWARE
595
FREQUENCY
CONTROL
INPUT N
M BITS
BINARY
ADDER
MSB
M-BIT
REGISTER
OUTPUT
FREQUENCY
MASTER
CLOCK­
Fe
M BITS
Fig. 17-5. Accumulator-divider structure
Accumulator Divider
The accumulator-divider method is based on the digital sawtooth
generator discussed in Chapter 13. The basic structure shown in Fig. 17-5
consists of a set of binary adders and a D-type register. The adders sum the
current register contents and the frequency control word together and feed
the result back to the register, which latches it up on the next clock pulse.
Thus, N is repeatedly added to the M-bit register, which overflows whenever
the accumulated sum exceeds 2 M -
I . The overflow frequency is the output
frequency which can be conveniently detected by monitoring the most significant
register bit. As with the sawtooth generator, the output frequency is
FNI2!vl, the same as the rate multiplier. Note that the division ratio must be
two or greater in order to use the MSB as the output.
The circuit can be considered to let every N /2 M th clock pulse through to
the output. When this ratio is an integer, which only occurs when N is a
power of two, the output pulse train is jitter-free. When it is not an integer,
it alternates between the integer values on either side such that the long-term
average is exactly equal to the fractional value. For example, ifM is 16 (2M is
65,536) and N is 384, the ratio 2M/N is 65536/384 or 170.66667. The
circuit will alternate dividing by 170 and by 171 with the latter occurring
twice as often as the former. Thus, the peak time jitter is never more than one
clock period. The peak-to-peakfrequency jitter in percent is simply the reciprocal
of N. Thus, at low output frequencies the jitter is very small but gets
worse as the output frequency is increased. Contrast this with the rate
multiplier, which has an essentially constant jitter regardless of output frequency.
The absolute frequency resolution of the accumulator divider is dependent
entirely on the register length, M, and can be increased without theoretical
limit. The relative resolution as a fraction of a particular output
frequency is simply liN for the N required to produce the frequency of
interest. The lowest possible output frequency is F/2 M , while the highest is
F/2 if the most significant register bit is the output. The master clock
frequency determines the time jitter, which is one clock period peak to peak.