of Microprocessors

Coding
Table 5-3. 68000 Addressing Modes
Name
Function
000000
001AAA
010AAA
011AAA
100AAA
101AAA
00
110AAA
RO
111000
aa
111001
aaaa
111010
00
111011
RO
111100
I I
111100
I /I I
111101
111110
111111
Data register direct
Address register direct
Address register indirect
Address register indirect with
postincrement
Address register indirect with
predecrement
Address register indirect with offset
Address register indirect with offset
and index
Absolute short (16-bit)
Absolute long (32-bit)
Relative with offset
Relative with offset and index
Immediate short
Immediate long
Unused
Unused
Unused
Quick immediate short
Quick immediate long
Operand is content of data register
DOD
Operand is content of address
register AAA
Operand is content of memory at
address in address register AAA
Operand is content of memory at
address in address register AAA;
after the instruction, the operand
length (1, 2, or 4) is added to
register AAA
Before the instruction, the operand
length is added to address register
AAA; ttle operand is content of
memory at address in register AAA
Operand is content of memory at
address in address register AAA
plus the 16-bit offset in the word
following the instruction
Operand is content of memory at
address in address register AAA
plus the content of register R
(either A or 0, either 16 or 32 bits)
plus an 8-bit offset; both specified
in the word following the instruction
Operand is content of memory at
address in the 16-bit word following
the instruction
Operand is content of memory at
address in the 32-bit long word
following the instruction
Operand is content of memory at
address in program counter plus
the 16-bit offset in the word
following the instruction
Operand is content of memory at
address in program counter plus
the content of register R (either A
or 0, either 16 or 32 bits) plus an
8-bit offset; both specified in the
word following the instruction
Operand is the content of the word
following the instruction
Operand is the content of the long
word following the instruction
These are reserved for future
expansion of the addressing
modes; the 68020 uses two of
them
A 3-bit field in some instructions
specifies an operand between 1
and 8 inclusive
An 8-bit field in some instructions
specifies an operand between
-128 and + 127.
Notes: 1. The first line under "coding" is the 6-bit address mode specification field found in all instructions
using generalized address modes. Each symbol represents a single bit in this field.
2. The second line under "coding," if any, represents additional bytes following the instruction that
contains additional addressing information. Each symbol represents a complete byte.
3. The "move" instruction contains two generalized address mode fields. If each requires additional
following words, the source address word or words come first.