of Microprocessors

380 MUSICAL ApPLICATIONS OF MICROPROCESSORS
RAW DAC OUTP UT
SAH CONTROL
SAMPLE
HOLD
SLEW-LIMITED SAH
EXPONENTIAL
RESPONSE SAH
TWICE THE AREA
~...._--~ ~
C-r-
fig. 12-8. Mechanism of slew-limiting distortion
and produces the output voltage. The effective offset volta2:e is dependent
only on the characteristics of A 1. This is normally important, since A2 is
optimized for low-bias current and typically has a high offset voltage (A2
could even be a simple FET source follower, which, in fact, is often done).
The problem occurs when the input voltage changes while the circuit is
in hold mode. When this occurs, Al goes into saturation, since its feedback
is from the previous input voltage. When S recloses, the capacitor is charged
at a nearly constant rate from the saturated output of A 1 through the switch
resistance until its voltage essentially matches the new input voltage. At this
point, Al comes out of saturation and the output settles.
Figure 12--8 shows how linear charging of the hold capacitor contributes
to distortion. For a one-unit change from one sample to the next, the
shaded error is one-half square unit. But for a two-unit change, the error is
two square units. Thus, the error is proportional to the square of the difference
between successive samples. It's not difficult to see how this can
generate a great deal of distortion, especially since slew times can easily reach
20% of the sample interval with this type of circuit.
If the step response is a normal inverse exponential instead of a linear
ramp, the error is directly proportional to the step size. This situation does
not cause any distortion, although it can affect the apparent overall signal
amplitude from the DAC when the steps are large (high signal frequency).
Figure 12-9 shows a simple SAH that can be designed not to slew
under any circumstances. If the values of Rand C are properly chosen, then
the voltage change across C will never exceed (or even approach) the slew rate
of the amplifier. For example, if the DAC produces ± 10 V and the R-C
time constant is 1.0 JLsec, then the maximum rate of change of capacitor
voltage (for a step of-lO V to + 10 V or vice versa) would be 20 viJLsec.
A standard high-speed op-amp such as an LM318, which is rated at 50
V/JLsec, would do nicely. One must be careful to limit the peak current
through the analog switch to a value less than its saturation current or a