of Microprocessors

742 MUSICAL ApPLICATIONS OF MICROPROCESSORS
to be dynamically changed in the data memory while the DMX-lOOO
program is running without interfering with it. The host can also read back
computed results or they can be sent directly to the D-to-A converters.
The computation logic is actually quite simple and consists of a 16­
word register file, 16-bit arithmetic logic unit (ALU), a 16 X 16 parallel
multiplier, and numerous "pipeline" registers. In the block diagram, all data
paths are 16 bits wide. The register file and ALU, which is implemented
with four 2901 type bipolar bit-slice chips, can select any pair of the general
registers as its inputs and can add, subtract, and, or, exclusive-or, etc., them
together. The ALU result can be written directly back into one of the general
registers and also appears on the Y bus. Other data paths internal to the ALU
for shifting and a 17th Q register are also present but not shown. The Y bus
leaving the ALU is the main output bus .of the machine and can be latched
into any of the data and delay memory source registers, the multiplier
operand registers, or the D-to-A converters. The S registers of the memories
hold a 16-bit address, while the W registers hold data to be written, if any,
on the next machine cycle. The D bus is the main input bus onto which data
read from either data memory, either half of the 32-bit product, or the A-to­
D converters may be gated. The D bus then wraps around to the ALU general
register inputs.
The DMX-lOOO operates with a machine cycle time of 200 nsec, and all
instructions require one machine cycle to execute. Every element of the
system, except the delay memory, can perform its function in one machine
cycle. Program memory is organized as a simple linear list of 256 sequential
instructions with no branching except for one implied branch from the end of
the program to the beginning. At the beginning of a sample period, four
machine cycles are used to allow external access to the memories, trigger the
ADCs, and other setup. Thereafter, instructions are executed sequentially at a
5-MHz rate until a halt instruction is encountered. At that point, the
program may either loop immediately to the beginning or wait for the next
sample pulse. Thus, one program loop is equal to one sample period. For a
completely full program memory with 256 steps, the maximum sample rate
is 19.3 ks/s. Program decision-making, which is necessary when computing
line segment approximations, for example, is implemented by conditional
execution according to the ALU condition codes. A failed conditional
instruction simply performs as a one-cycle no-op.
Programming the DMX-lOOO consists of establishing a bit pattern for
each instruction in the sample loop. The 32 instruction bits are divided into a
number of fields. For example, two 4-bit fields and another 3-bit field
determine which general registers or other data sources are selected for the
ALU inputs, while a 6-bit field determines the ALU operation. Additional
fields determine which of the Y bus registers are loaded and which of the D
bus registers are selected for the current machine cycle. Unlike most generalpurpose
computers, each element of the DMX-lOOO can be performing