of Microprocessors

DIGITAL-TO-ANALOG AND ANALOG-TO-DIGITAL CONVERTERS 257
bers, it should be possible to keep 880 JLsecl20 JLsec=44 channels refreshed,
and it would be realistic to support as many as 64 with a 2-time constant
recharge period. Larger capacitors (to minimize switch glitch error) yield a
slightly increased channel capacity because, although the longer drift time is
cancelled by longer recharge time, the DAC settling time becomes less of a
factor. Thus, it would be worth considering the LM324 as the channel
output amplifier in a system with 64 or fewer channels.
Refresh Logic
As with dynamic memory in a microcomputer system, refreshing the
multiplexed DAC presents some problems that partially offset the lower cost.
One method of handling the refresh requirement would use the microcomputer
system's interval timer to interrupt the program periodically.
The interrupt service routine would then update all of the DAC channels
from a table in memory and return. Whenever the main program actually
wanted to change a DAC channel output, it would directly update both the
output and the corresponding table location.
Although easily implemented, this scheme has two serious difficulties.
One is the time stolen from the main program for the refresh operation.
With 64 channels and bipolar channel amplifiers, all available time would be
used to refresh the DAC. Even with FET amplifiers, a substantial amount of
time may be stolen. Also, if the microcomputer is stopped or a nonmusicplaying
program is executed, such as the system monitor, the DAC refreshing
stops and the channel output voltages drift away to undefined levels. If
the synthesizer were not shut down, the drifting voltages could produce a
really raucous racket! Thus, it is advantageous to perform the refresh automatically
with some scanning logic-or a logic replacement microprocessor
dedicated to the refreshing operation.
An Intelligent DAC?
A 6502 and three additional support chips would make a superb
multiplexed DAC controller. Figure 7-25 outlines such a unit that could
support up to 128 channels. The 6532 interface chips simultaneously provide
two 8-bit liD ports, 128 bytes of readlwrite memory, and one interval timer
each. These provide all of the interfacing needed between the control
processor and the using system, DAC, and analog multiplexor. The 2716
PROM provides nonvolatile program storage for up to 2048 bytes, ample for
a very sophisticated refresh routine indeed. These four ICs could be expected
to cost less than $50 total, which is less than 40 cents per channel.
Using a microprocessor for refresh control offers a lot more advantages
than a low package count, however. The using system, for example, can
communicate the 12 bits of data and 7-bit channel address on a byte basis