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DIGITAL-TO-ANALOG AND ANALOG-TO-DIGITAL CONVERTERS 267<br />

- 3<br />

DM2504 EOC 23<br />

BTi<br />

21<br />

2 MHz o------!l- CLOCK 811<br />

20<br />

810<br />

19<br />

START~ 89<br />

START 88<br />

---u--<br />

18<br />

17<br />

87 16<br />

86<br />

9<br />

f ENA8LE 85 8<br />

84<br />

+5 7<br />

83 6<br />

B2<br />

470 J1,<br />

5<br />

81<br />

~ DATA<br />

4<br />

80<br />

T<br />

I 2 3 4 5 6 7 8 9 10 111121<br />

8118108988 B7 8685 B4 83828180<br />

10 K 15 - I ref<br />

~<br />

DAC= 312<br />

+Vref 10 K 14<br />

110 V.)<br />

Lti- lre/ lout I lout 2 Vee Vee Ceomp Vlth<br />

19 18 3<br />

7~3 t<br />

f;f,~ +5<br />

17ticJI6<br />

_15 0 . 01 }JF<br />

1<br />

=<br />

I +<br />

OR<br />

ffi2 4 ~ "IN4148 +15<br />

ANALOG<br />

TO<br />

-IOTO+IOV.<br />

5K +15 -15 (KEEP THIS<br />

NODE SMALL!<br />

END OF CONY.<br />

BTr (TWOS COMP.I<br />

811 (OFFSET 8IN.)<br />

810<br />

89<br />

88<br />

87<br />

86<br />

85<br />

84<br />

83<br />

82<br />

81<br />

80 LS8<br />

Fig. 7-34. 6-tLsec 12-bit ADC using DAC-312<br />

One very reasonably priced (under $5 for Y2 LSB linearity) unit is the<br />

ADC0801 series from National Semiconductor. It uses a resistor string DAC<br />

internally along with CMOS circuitry and is capable <strong>of</strong> conversion times in<br />

the 60-100-J.Lsec range. It operates entirely from a +5 V power supply and<br />

accepts analog input voltages from 0 to + 5 Vas well. The 8-bit output value<br />

goes through an internal tri-state buffer and thus can be connected directly to<br />

the microprocessor data bus in a small dedicated system. Figure 7-35 shows<br />

a typical hookup for the ADC0803, which is the Y2 LSB grade unit.<br />

Although the analog input is a very high impedance when the unit is idle, it<br />

becomes finite and variable during conversion and therefore should be driven<br />

from an op-amp output. Internally, a 2-to-1 voltage divider provides a<br />

+ 2. 5-V reference from the + 5-V power input, but an external reference can<br />

be connected to the Vrefpin if desired. The analog input range is twice the<br />

reference voltage but must not be larger than the supply voltage or negative.<br />

The sequencing clock is generated by a built-in RC oscillator and a<br />

conversion requires from 66 to 73 clock cycles to complete. The components<br />

shown will produce approximately 1 MHz or an external clock can be<br />

connected to pin 4. A negative pulse on the start input while chip select is

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