of Microprocessors

652 MUSICAL ApPLICATIONS OF MICROPROCESSORS
2. The range of the quotient is equal to the range of the dividend divided
by the range of the divisor. This means that the number of bits in the
integer part of the quotient is equal to the number of integer bits in the
dividend minus the number of integer bits in the divisor.
3. The resolution of the quotient is equal to the resolution of the dividend
divided by the resolution of the divisor. This means that the number of
fraction bits in the quotient is equal to the number of fraction bits in
the dividend minus the number of fraction bits in the divisor.
Examination of these rules reveals that one just can't win with division.
For example, if both operands have the same word size and both are fractions,
the one used for the dividend must be padded on the right by N zeroes,
where N is the fraction size desired in the quotient. Thus, if the desired
resolution is the same as the operands, the dividend must also be smaller than
the divisor so that the range of the result is less than unity. The only way to
cover all possible combinations (except a zero divisor) of two N~bit fractional
operands without overflow or loss of resolution is to use a dividend 4N bits
long and a divisor 2N bits long. The dividend used in the arithmetic operation
would be the actual N dividend bits padded on the left by N zeroes (or
sign bits if signed) and padded on the right by 2N zeroes. The divisor would
similarly be padded by N zeroes on the right. The 2N quotient bits then
allow N range bits (N-1 for signed operands) and N resolution bits. Fortunately,
when division is needed in signal processing (usually for computing a
scale facror), the values of the operands will be known well enough to avoid
trouble.
Required Arithmetic Instructions
Regardless of whether hardware instructions are available or an arithmetic
subroutine package is being used, there is a certain "complete set" of
operations that is needed for straightforward signal-processing computation,
Such a set is usually built around a particular word length. When hardware
instructions are available, this is usually the machine's accumulator word
length. Some of the operations produce or process double words, which then
require a pair of registers to hold. In fact, classic single-accumulator computers
usually had an accumulator extension or multiplier/quotient register,
which was used to hold the low order half of double words.
For illustrating a fixed-point arithmetic package with the 6502, a word
length of 8 bits will be used for simplicity, although 16 bits would be more
practical in high-quality synthesis. Since the 6502 has very few registers, two
bytes are set aside in memory for a double-word accumulator. The other
operand if singl,e byte or its address if double byte is passed to the subroutine
in a register, Following is a list of the arithmetic operations and the operand
word lengths that would be expected in such a package: