22.09.2015 Views

of Microprocessors

Musical-Applications-of-Microprocessors-2ed-Chamberlin-H-1987

Musical-Applications-of-Microprocessors-2ed-Chamberlin-H-1987

SHOW MORE
SHOW LESS

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

266 MUSICAL ApPLICATIONS OF MICROPROCESSORS<br />

presented by the DAC. Because the speed <strong>of</strong> most DACs is determined by the<br />

output amplifier, it would be nice ifit could be eliminated. This, in fact, can<br />

be done easily if the connection to the comparator is slightly altered. Rather<br />

than using a voltage comparator with a voltage output DAC and an unknown<br />

input voltage, what is desired is a current comparator that can be connected<br />

directly to a current-output DAC. The unknown voltage can be converted to<br />

a current by use <strong>of</strong> an accurate series resistor.<br />

True current comparators with sufficient accuracy are not generally<br />

available but the configuration shown in Fig. 7-33 is virtually as good and<br />

uses the same LM31l-type voltage comparator. A mismatch between the<br />

DAC current output and the unknown current will tend to pull the 311<br />

inverting input away from ground, thus switching the comparator according<br />

to the direerion <strong>of</strong> the mismatch. The two diodes across the comparator<br />

inputs limit the voltage swing for large mismatches, thereby maintaining<br />

high speed (small voltage swing minimizes effect <strong>of</strong> stray capacitances) and<br />

keeping the current output DAC happy.<br />

Figure 7-34 shows a complete 12-bit ADC circuit that is easy and<br />

inexpensive to build and is very fast. A DAC-312 current output OAC is<br />

combined with a DM2504 successive approximation register (made by<br />

National Semiconductor and others) and the comparator circuit just described<br />

to yield a conversion time <strong>of</strong> only 6 f-Lsec. The 2-MHz clock<br />

sequences the successive approximation at the rate <strong>of</strong> one trial per clock cycle.<br />

A conversion is started by a negative-going pulse at the START input and<br />

completion is signaled by EOC going low. The analog input impedance is<br />

5K but varies somewhat during the conversion and should be driven by a<br />

high-speed op-amp output. If a 12 f-Lsec conversion time is acceptable, a<br />

74C905 CMOS successive approximation register can be used in place <strong>of</strong> the<br />

DM2504 and the clock slowed to 1 MHz.<br />

Complete Hybrid module ADC circuits using the successive approximation<br />

technique have been available for many years, but their cost has<br />

always been much higher than an equivalent circuit constructed from a DAC,<br />

a comparator, and a successive approximation register. Until recently, all<br />

monolithic IC ADCs were <strong>of</strong> the much slower dual-slope type. Even now, 8<br />

bits is the highest resolution <strong>of</strong>fered in an integrated circuit AOC.<br />

UNKNOWN<br />

INPUT<br />

VOLTAGE<br />

R<br />

+5V<br />

I kfi<br />

TO<br />

>----.. ~~~~~S~~iTION<br />

LOGIC<br />

Fig. 7-33. Analog circuitry for a high-speed ADC

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!