of Microprocessors

DIGITAL HARDWARE 605
1. Sixteen independent oscillators are simulated.
2, Each oscillator has an independently programmable waveform.
3. Moderately high tonal quality (50 dB SiN) is desired.
4, Waveforms may be dynamically updated without glitching the output.
Although the last feature may be impractical in a single-channel oscillator,
its cost is divided by 16 when multiplexed.
A typical nonmultiplexed digital oscillator has a timing diagram something
like Fig. 17-11A. Immediately following the active clock edge, things
happen and signals change. A finite time later, everything settles down and
remains stable until the next active clock edge. The time between settling
and the next clock is "wasted" because nothing is happening.
Multiplexing utilizes this idle time by assigning it to the "data" for one
or more additional oscillators as illustrated in Fig. 17-11B. Such data consist
of the frequency control word, the state of the counter in the frequency
divider, and the waveshaping table. Essentially, the data are read from a
memory, the next state is determined by the logic, and the result is written
back into the memory and an output circuit. The entire sequence for a
particular oscillator takes place during one minor clock cycle. A major clock cycle
consists of N minor clock cycles, where N is the number of oscillators
simulated. There will, in fact, be a minor clock cycle counter that identifies
minor cycles within a major cycle. Thus, the sample rate for each oscillator is
the major clock frequency, while the throughput rate for the computation logic
is N times the sample rate or the minor clock frequency.
Before proceeding further, the implementation technique for the
oscillator must be determined. One thing to keep in mind is that the minor
cycle frequency is N times the effective clock frequency for a particular
oscillator. This eliminates the variable sample rate techniques described
earlier because they all require a clock frequency on the order of 5 MHz. To
multiplex these according to the specs above would require a throughput rate
of 16 x 5 or 80 MHz, somewhat beyond the capabilities of standard logic.
Thus, a fixed sample rate approach will be used. In the example system being
FREQUENCY
CONTROL IN
EXTERNAL
EXTERNAL
ADDRESS SELECT DATA IN WRITE
20
FREQUENCY
CONTROL
WORO
REGISTER
OUTPUT
SAMPLE
CLOCK
Fig. 17-12. Nonmultiplexed oscillator organization