of Microprocessors

DIGITAL HARDWARE 607
discussed, the sample rate will be set at 62.5 ksls, which when multiplied by
16 yields a throughput rate of 1.0 MHz. This equates to a major cycle time of
16 fLsec and a minor cycle time of 1. 0 fLsec.
Hardware Structure
The first step in designing the multiplexed oscillator is to draw a
detailed block diagram of the equivalent nonmultiplexed oscillator as in Fig.
17-12. Note that the data input to the oscillator logic comes from a register
and that the DAC output goes to a sample-and-hold, which acts like an
analog register. The 20-bit word length chosen for the accumulator allows a
frequency resolution of 0.3% at 20 Hz and 0.005% (equal to typical crystal
oscillator accuracy) at 1 kHz. The lO-bit word length for waveform address
and data gives a SiN ratio of greater than 50 dB for the tone.
In converting to the multiplexed oscillator shown in Fig. 17-13, one
replaces all registers with memories, each consisting of N words and addressed
by the minor clock cycle counter. In the case of the waveform tables,
an N times larger memory holds all of the waveforms, and a particular section
is addressed by the minor cycle counter. Thus, the frequency control word
becomes the frequency control memory, which is 16 words of 20 bits, and the
accumulator register becomes the accumulator memory, which is the same size.
The waveform memory grows to 16K by 10 if each oscillator is to have a
different waveform. The final outputs now come from 16 SAH circuits,
which are addressed like a 16-position analog memory.
Before determining the timing diagram, components must be selected
for the various blocks. Such a selection must be made on the basis of speed
and cost. Obviously, memories that require a 2 fLsec cycle time cannot be
used, but, on the other hand, a 50-nsec bipolar memory would be overkill for
the waveform tables. For this example, the waveform memory will use 10
type 4116 MOS dynamic RAMs, which are organized as 16,384 words of 1
bit each. Although dynamic RAMs are the cheapest form of memory
available, they require periodic refreshing to retain data. Refreshing is
accomplished simply by reading at least one location in each of the 128
blocks of 128 addresses every 2 msec. Since the oscillators are constantly
scanning through the waveform memory, it will be automatically refteshed
provided that zero frequency (or an exact multiple of 7.8125 kHz) is not
programmed fot all of the oscillators simultaneously.
Frequency control words and accumulators will be stored in 10 type
7489 bipolar memories, which are conveniently organized as 16 words of 4
bits each. The address selector for the waveform memory uses four type
74153 dual one-of-four multiplexors, which simultaneously select between
accumulator and external addresses and between lower and upper 7-bit halves