of Microprocessors

658 MUSICAL ApPLICATIONS OF MICROPROCESSORS
however, did know how to multiply and as it turns out their hardware
methods are highly efficient in software too.
Figure 18--4 illustrates the shift and add multiplication algorithm.
Two "registers" are involved; the multiplicand register which is 8 bits long,
and the 16-bit pseudoaccumulator. Prior to multiplication, the multiplicand
is placed in the multiplicand register, the multiplier is placed in the low
order half of the pseudoaccumulator, and the high order half is cleared. A
shift and add cycle consists of shifting the entire pseudoaccumulator right
one bit and testing the least significant bit shifted out. If this bit is a zero,
the cycle is complete. If the bit is a one, the multiplicand register is singleprecision
added to the upper halfof the pseudoaccumulator. This addition may
overflow, so it is important to bring in the carry flag when the next shift
cycle is done. A little thought will reveal that as the multiplication progresses
the multiplier is "eaten away" at its right end and the product grows
downward as the multiplier is shifted out. A total of 8Y2 cycles are needed to
complete the operation. The half-cycle is a final shift of the pseudoaccumulator
to bring in a possible overflow from the last addition and properly
align the product.
The above algorithm is different from many that are published in that
the product is shifted right and the multiplicand stands still rather than
vice versa. Efficiency improvement is due to both product and multiplier
shifting being handled simultaneously and the fact that only single-precision
addition of the partial products is required. If the upper part of the pseudoaccumulator
is not cleared prior to multiplication, its contents wind up being
added to the product. Since this may be useful and actually saves a slight
amount of time, the unsigned multiplication routine provides an alternate
entry point that skips clearing the product. Note that binary multiplication,
even with the "free add" included, cannot overflow.
Unsigned binary division, illustrated in Fig. 18-5, is precisely the
reverse of multiplication. The algorithm can be described as a "shift and
conditionally subtract" procedure, opposite that of multiplication. Again,
DIVIDEND
,
SHIFT ENTIRE REGISTER LEFT
REMAINDER
QUOTIENT
" \~-------.f1
ij
I I I Ii: !
DIVISOR
SUBTRACT IF
RESULT IS
NOT NEGATIVE
: I
OUOTIENT BITS
1 FOR SUCCESSFUL
SUBTRACT
Fig. 18-5. Shift-and-subtract division