of Microprocessors

162 MUSICAL ApPLICATIONS OF MICROPROCESSORS
FUNCTION CODE
ADDRESS BUS
ADDRESS STROBE
READ/WRITE
DTACK
DATA BUS
70-, ~
-'-:::~+-7D
60 ...... I....
,--+---1-----1'
____--+-_-""'--,60
70- 1- ...... 1+-0
( VALID )
y~--~/\
FULL SPEED CYCLE
I
X
\ ,
\ ? ,
15-1 ,......../15 ...... ,95-1
"',,').
~
( VALID )-
y
I WAIT STATE CYCLE
I
Fig. 5-4. Motorola 68000 write cycle
Like all microprocessors, the 68000 has provisions for waiting on slow
memories, dynamic RAM refresh, and so forth. The others, however, have a
wait signal, which must be activated to cause such a wait; ignoring the wait
signal will allow full speed operation. The 68000 instead uses a data transfer
acknowledge signal (DTACK), which must be driven to cease waiting and
allow the cycle to complete. Motorola literature, which is geared toward
large-system implementation, devotes a great deal ofspace to how this signal
should be driven, which makes 68000 bus cycles appear to be much more
complex than they really are. In reality, DTACK can be treated as simply the
inverse of wait in a simple system. In systems with all static memory
requiring no wait states, DTACK can simply be tied to ground, and the bus
cycles will proceed at full speed.
In any case, DTACK is sampled at the beginning ofState 5. Ifit is low,
the cycle proceeds, and read data is latched in the microprocessor at the
beginning of State 7. If DTACK is high when sampled in State 5, States 4
and 5 are repeated indefinitely until it is seen to be low. Thus, waiting is in
increments of 125 nsec (assuming an 8-MHz clock), a much smaller penalty
than with the 6502. For static memories (such as ROM), the allowable read
access time is about 290 nsec, whereas, for dynamics (which are triggered by
address strobe rather than an address change), it is about 235 nsee. Neithet
requirement puts much stress on modern memory components, so zero wait
state operation should generally be possible.
Figure 5-4 shows a write cycle, which is quite similar to the read cycle
just discussed. During State 2, simultaneously with Address Strobe, Read/
Write goes low to signal a write cycle. The data strobes are not activated until
State 4, at which time data on the data bus is guaranteed to be stable. When
a word is written, both data strobes are activated to cause writing into both
halves of the word. However, only one is activated when a byte write is to be
performed. Memory must be organized into two 8-bit halves such that
writing only occurs when the corresponding data strobe is activated in