of Microprocessors

DIGITAL HARDWARE 623
into a filter bank spectrum analyzer by suitable setting of control words and
signal memory addresses. The pseudo-DAC module simply serves as a
method for the control computer to write directly into the signal memory.
As might be expected, the system is performance limited by the two
memories. Although the control memory is shown as a system-wide resource,
in reality it is part of the individual modules. Only the control computer
requires access to all of the control memory. Modules need only access the
portion that holds their own control words. Control memory design, then, is
equivalent ro that employed in the multiplexed oscillators described earlier.
Thus, the control memory does not limit performance as modules are added.
The signal memory is a different story, however. Every module must be
able to access any part of it at random. In fact, the total number of read
accesses per sample period is equal to the total number ofsignal inputs in the
system. Likewise, the number of write accesses per sample period is equal to
the number of signal outputs in the system. The total number of words in the
memory is also equal to the number ofoutputs. Thus, at first glance, N + M
memory cycles must be performed in a sample period, where N is the number
of inputs and M is the number of outputs. The proposed system had provisions
for 288 inputs and 288 outputs. A straightforward time-multiplexed
signal memory would need a cycle speed of 27 nsec to get all 576 accesses
accomplished in a 16-f.Lsec sample interval.
The cycle rate can be nearly cut in half if writing is performed in an
orderly fashion. This is quite reasonable, since every word is written each
sample period and write addresses are preassigned to the modules. In order to
save time when writing, the memory array is organized such that several
write ports are formed that can be written into simultaneously. In the
proposed system, the signal memory consisted of 18 blocks of 16 words each.
Only 16 write cycles were therefore necessary to update the entire memory.
By using the block write, the number of memory accesses per 16f.Lsec is cut
down to 304, which allows a 50-nsec read cycle and a lOO-nsec write cycle; a
practical figure for conventional logic.
The number of signal inputs in the system is therefore limited by signal
memory speed. The only way to overcome that limitation without sacrificing
interconnection flexibility is to completely duplicate the memory so that two
real read access ports are available. The same data would be written into the
same addresses in both memories simultaneously. Reading would be independent
with half of the modules reading from one memory, while the
remainder read from the other half. The memory throughput capability
would therefore be doubled. Memory splitting without duplication is also
possible if a communication module is defined that can transfer selected signals
from one-half of the system to the other.
Signal-Processing Computer
In spite of the flexibility of a modular digital synthesizer, nothing
matches the generality of an ordinary computer in sound synthesis and