of Microprocessors

256 MUSICAL ApPLICATIONS OF MICROPROCESSORS
refresh interval can minimize the effect, polystyrene should always be used
for the hold capacitor dielectric.
The capacitor size is largely determined by the required update time
and the on resistance of the analog switch. Note that some switches with an
otherwise low resistance may require external series resistance to limit the
current when large changes in output voltage occur such as from -10 to
+ 10 V. Without limiting resistance, a 50-ohm switch would try to conduct
nearly half an amp (if the DAC output amplifier could deliver it) when
switched on. For purposes of calculation, a total switch and limiting resistance
of 400 ohms will be assumed.
Part of the update time is spent waiting for the DAC to settle. With a
decent output amplifier on the DAC, this can be around 5 p.sec. Thus, if the
total update time is to be 50 p.sec, then 45 are available for capacitor
charging. Assuming a worst-case transition of the full 20-V range, a worstcase
error of one-half the resolution of a 12-bit main DAC would require the
capacitor to charge within 2.4 mV or about 0.012% of its final value. With a
normal negative exponential charging curve, at least 9RC time constants will
be tequired to update the capacitor that accurately. The RC time constant
therefore should be 5 p.sec or less, meaning that C can be no larget than
0.016 p.F. Unfortunately, this is not always large enOllgh to swamp out the
effect of feedthrough glitch in the analog switch. Larger capacitors up to
perhaps 0.1 p.F (about the largest polystyrene value available) may be usable,
however, if large voltage steps are avoided or several refresh periods for final
channel settling is acceptable.
Channel Output Amplifier
The channel output amplifier to a large degree determines the refresh
period, since its input bias current is normally the largest contribution to
leakage from the storage capacitor. This problem may be easily circumvented
by using one of the newer FET input op-amps that have vanishingly small
bias currents. However, these tend to have larget offset voltages than bipolar
input stage devices and cost more. So, as an exercise, let us determine just
how bad the situation would be with a standard bipolar op-amp.
The LM324A is a popular quad op-amp with an unusually low bias
current of 45 nA and a typical offset voltage of 2 mV, a little less than
one-half the step size of a 12-bit, ± lO-V DAC. With a hold capacitor of
0.016 p.F calculated previously, the drift rate due to bias current will be 2.8
V/sec. Thus, if drift is to be held to less than one-half the DAC step size (2.5
mY) between refreshes, the refresh interval should be less than 880 p.sec. A
refresh operation could be expected to take considerably less time than a full
update operation, since the capacitor voltage change is normally very small.
A 20-p.sec reftesh time, for example, would allow 5 p.sec for DAC settling
and a liberal three time constants for capacitor recharge. With these num-