of Microprocessors

154 MUSICAL ApPLICATIONS OF MICROPROCESSORS
I----CLOCK CYCLE = I }Jsec---I
CLOCK PHASE I PHASE 2 \'-- _
1-300-1
ADDRESS BUS Y// / / / / / / /X VALID
'41'// "/
READ/WRITE~4 I///l///
I 100 1
DATA OUT 'lZ/Zl/ftAW//l/l/7/AI.._...:.V;::AL::;;ID:---,X,,- _
Fig. 5-2. 6502 write cycle timing
The write cycle in Fig. 5-2 is quite similar. The address and write
indication settle during Phase 1, and the data to be written is put onto the
data bus by the processor at the beginning of Phase 2 and held until the start
of the next Phase 1. Devices written into will, therefore, have to look at
Phase 2 and read/write to decode a valid write operation, These are the only
cycle types; all input and output is memory mapped.
Being so simple, there must be limitations and indeed there are a
couple. A ready line is available for slow memories to request additional time
for access. If the 6502 sees a low level on this line at the beginning of Phase
2, it will delay reading the data bus until the next cycle. The catch is that
write cycles cannot be extended with this signal. 3 Actually, at the present
state of the art, there is little if any cost advantage in using such slow
memory. In fact, if only a couple hundred extra nanoseconds are needed, it
would be better to reduce the clock frequency anyway. The other catch is that
if "transparent latches" (level clocked) are used for output registers and the
clock is Phase 2, then glitches at the outputs are likely when written into.
The problem can be solved by either using edge-triggered registers (trigger at
end of Phase 2) or by generating a delayed Phase 2 that does not become
active until the data bus is stable.
One unusual property of the 6502 is that the address bus cannot be
disabled for direct memory access operations. This and the fact that there is
no hold pin like on other microprocessors and write cycles cannot be stopped
would seem to make DMA difficult, if not impossible. Actually, a little
study of the bus timing reveals that if three-state buffers are added to the
address lines and 400-nsec memory (or a slight clock slowdown) is used, then
transparent DMA becomes possible. Transparent means that the processor is
unaware that DMA is taking place and continues to run at normal speed.
This would be accomplished by using Phase 1 for DMA operation and
allowing the processor to use Phase 2 normally for data transfer. Since the
processor never drives the data bus during Phase 1, only the processor's
address bus would have to be disabled (via added three-state buffers) for
DMA during Phase 1. The result is that a guaranteed continuous DMA rate of
3 A new 6502 version consrrucred wirh CMOS transisrors rhar became available in 1984
does honor rhe ready signal during wrire cycles.